I really appreciate the responses. I should mention I'm using LabVIEW 8.6 for my current effort as it appears that there have been significant changes with FPGA between 8.6 and 2010.
In my current programs, I use 1 DMA to send data down to the FPGA and another DMA to get data back.
For sending large numbers of parameters from the host to the FPGA without using a lot of front panel controls, I'd put three controls on the front panel: a data value, an index, and a boolean indicating that the value has been read (you could also use an interrupt). [snip]
That's two interesting approaches. I think the DMA would be less effort on the PC side (send and forget versus needing to check the boolean?) and allow the setting of multiple values at once, but the DMA would require sending two values (index and value) or reserving bytes for index and value. I tried compiling each:DMA
FIFO is 63 elements long of U32.
I didn't see much difference in resource usage.
By using globals, you can slow down your FPGA since sections of code will be blocked until the other section accesses it. There are times that I used them (non critical timing), but try to avoid them.
You want to avoid arbitration - multiple loops all trying to access the same resource, such as a functional global.
Okay, globals are still to be avoided.
A memory block acts a lot like a global variable in practice, but it is an efficient way to store and share data on the FPGA, and you can avoid arbitration if you have only one location where you read and one location where you write. Similarly, you can choose to have your FIFOs implemented in memory.
It appears the memory is what I should have used for in a one-write-location, multiple-read-location situation. Globals, unfortunately, are nice in that it's clear what data I'm trying to access. The only ways I can see to make it clear what is being accessed in memory is, 1) to create single-element memory blocks for every piece of internal data to be stored, 2) to create an enumerated typedef to provide the indeces of the data in the block, or 3) to create a subVI to read each data element. (I'm liking 1 or 2...)
Note that there's a difference between a DMA FIFO, which passes data between the FPGA and host, and a FIFO that only passes data around the FPGA.
How is a Target Only FIFO different than a DMA FIFO? I've not been able to locate anything on NI's website or the help files.