How about debugging of reentrant VIs on LabVIEW RT (Real Time)? I often need that, or, as a temporary workaround, the ability to specify the target on which to open a VIs front panel on. The latter would entail that reentrant VIs should maintain a copy of their front panels, even on RT, and that this front panel could be spawned on a remote Host, and then connected to the block diagram of the reentrant Vi on the RT target.

Cheers,

Steen

We have a remotely deployed cRIO system that requires nothing short of an Act of God to physically access. For the past couple of months we have been trying to troubleshoot a complete cRIO lockup that requires us to power cycle it via a web-based relay between the cRIO and its power supply. This has been happening every 2-5 days on average. The architecture itself is a rtexe that dynamically loads a number of PPLs specified in a config file via Start Asynchronous Call and I've been able to run a similar system on benchtop for weeks without issue.

Physical architecture is a cRIO-9042 with a GPS module, a couple of 9220s, and 2x FD-11601s daisy chained using DAQmx to acquire data from ~70 channels. Software-wise, this particular system launches 6 unique PPLs: (1) performs DAQmx acquisition and publishes its values via a User Event, (2) registers for the DAQ data event and base64 encodes the data and does some other formatting on it to prepare it for network transmission which it sends to a named queue read by another PPL that performs the network transmission, (3) also registers for the DAQ data event and calculates the detection of transient events then sends those results via the same named queue read by the network transmission PPL, (4) one that performs the network transmission, (5) one that reads weather station data via Modbus TCP and formats/sends it to the network transmission PPL via the named queue, (6&7) the same FLIR camera PPL is launched twice but each one targeting a different networked camera which then parses the image and sends it to the network transmission PPL via named queue.

I've monitored memory usage with /proc/meminfo as well as monitoring the specific lvrt application via /proc/(lvrt_proc_id)/status. There seems to be no substantive change in memory over time (i.e., assumedly no leaks) and cRIO CPU usage varies between 10-20% per core, although average seems to be around 13% per core. I do see a very rapid increase in context switches, both voluntary and nonvoluntary, on the order of ~500 voluntary and ~5 nonvoluntary per second, but I have no frame of reference to determine if this is "high" or whether this is even a problem. My Linux knowledge is relatively limited so maybe there's another thing I should be monitoring of which I'm unaware.

Does anybody have any anecdotes about situations where they've had cRIOs crash sporadically without seeing a memory leak and what they did to troubleshoot/debug it? The disappointing thing is the logs I pull from MAX don't even show that anything happened -- it's basically a complete system freeze (doesn't reply to pings from other computers either). I see what I believe to be the power cycle event in the logs once I force the relay on the supply to open/close, but even if I wait days between it going non-responsive and power cycling it I won't see anything representative of the lockup in the logs except the power cycle. We're going through the arduous process of trying to gain physical access to the cRIO so we can look at the status lights on the front and measure the supply voltage when it's frozen, but that'll probably be another couple of weeks before we get permission and I'd love to have a checklist of other potential things we can try in our limited window of time we have physical access.

Unfortunately I can't post any screenshots, let alone any code, due to the nature of the deployment which is why my question is so general and I'm just soliciting some stuff to throw at the wall hoping that it sticks. I've started logging max queue size for the data transmission queue to the cRIO HD, but it consistently remains low enough not to be a concern. We also don't see any delay in ingestion of the data by the database computer -- all of the received timestamps and data are updating completely as expected until the cRIO locks up.

Whether anyone replies to this or not, I feel better that I've ranted so thank you for the mental relief!

I want to use one dimensional lookup table for interpolation in FPGA.vi, I am using U16 data type and one lookup table can store 40960 data and I need to store 7 million data. Currently I have inserted only 16 tables and the RAM resources are not enough. My compilation tells me that one lookup table takes up 19 RAM resources (my device has a total of 325 RAM resources).

But on the lookup table it shows that one table uses only 80KB of storage, while on the official website the CRIO-9043 has a RAM size of 2G!

I don't know how to solve this problem. Attached is my program, sorry it's only in Chinese!

15.vi

I know that using User Controlled I/O Sampling Acquire Faster than an I/O Node, but now one of my loops does not involve an I/O Node, and in this loop my program may be too complex to meet the 500k requirement when using the timed loop program as shown.

Is there any other way to write a timed loop?
Please provide me some help! Thanks!

I am currently trying to work with an RS485 device connected to my sbRIO9627 RS485 port. The manufacturer developed a LabVIEW library to communicate with the device with a ModBus RTU protocol, requiring both NI-VISA and NI-Serial installed on the target. It worked fine at the beginning, then after a necessary format of the RT target, I am now not able to install the NI-serial drivers on the sbRIO as before, and the communication fails with a timeout error, but I still don't get any deploy or execution error.

The NI-serial drivers do not appear in the list of items I can install during the software installation on the target.

Does anyone have a clue about this? 

I am currently working with LabVIEW 2020, Linux RT image 21.0, NI-MAX 21.0f0, and I have to stick to LabVIEW 2020. 

Thanks in advance for your help

I am trying to install an external package, OPENG ZIP library, on an sbRIO 9627. I currently work with LabView 2021, I installed on the sbRIO RT Linux version 21.8 and LabVIEW 2021, but the OPENG ZIP library does not appear in the list of available packages in the MAX. I already enabled the offline installation and installed the library on my system via VIPM 2021, I can see it in LabVIEW and correctly write code using the library VIs. 

Moreover, everything was working smoothly on LabVIEW 2019.

How can I solve this problem? 

Thanks in advance

We have a PXI-system with a PXIe-8821 controller running LabVIEW RT (PharLap). On this controller we have a deployed LabVIEW developed application. So all standard so far.

From time to time the application ends up in an erroneous state. Since the overall system is relatively complex and used as a development tool for another system, it is tedious to detect and debug each situation that leads to an error. So the current solution is to regularly reboot the controller. Both at a fixed time interval and when the controller is suspected to be in an erroneous state.

To achieve this remotely we send a reboot command by spoofing the HTTP POST command sent when clicking on the "restart button" in NI's web based configuration GUI. I was surprised that this worked, but it does, and it does so pretty well.

But there is an issue: we have an instrument that can get upset if the reference to it isn't closed down properly. And since this reboot on system level harshly close down our application this has increasingly started to become an issue.

So I have two questions:

1. Is there a way to detect that a system reboot is imminent and allowing the LabVIEW application to act on it? Closing down references and such.
2. Is there another way to remotely reboot a controller? I am aware of the built in system vi's but those are more about letting the controller reboot itself. What I'm looking for is a method to remotely force a reboot.

Any input is most welcome!

I need to deploy a startup.rtexe into my cRIO-9049 (from LabVIEW Project Explorer or CLI, whatever), and I need to use the ./nilvrt start and ./nilvrt stop commands to start and stop the RT App respectively, at will. I noted that it is mandatory to reboot the cRIO after deploying the .rtexe to use the  ./nilvrt start and ./nilvrt stop. However, I must avoid rebooting the cRIO (because of my customer requirements). I was trying to find a setting for this, but the only file I found related to the startup.rtexe is the /etc/natinst/share/lvrt.conf file with the token RTTarget.LaunchAppAtBoot. This key is set to True when the Run As Startup option is selected from the LabVIEW Project Explorer. I put this key in False to check if this allows me to run the RT App without rebooting the cRIO, but this did not help 😔.

Is there another config file to be modified in order to support what I need to do? 

Is it completely necessary to reboot the cRIO to recognize the new .rtexe and use the ./nilvrt start and ./nilvrt stop commands?

Thanks!

A newbie question - say, I have a compactRIO running Linux Real-Time system and it runs my .rtexe set as startup

at the boot. I wonder if there is a way to execute this .rtexe arbitrarily from CLI or by any other means, so you can

actually have a few .rtexe on the system and pick and choose which ones to run at will?

Ni-Max and LV see the 9035 , I have RT and FPGA licenses , Ni-Max says I have all the s/w , but , I cant find how to do a test in Ni-Max like the examples I see on NI.com

I am connected via USB , ultimately it needs to be connected via Ethernet ....

I know I am asking a lot at the moment , but , anything that can get me going would be fantastic.... 

Regards

Dan

I have Florence installed with opkg and I also made a little bash script to call it. When I execute it from CompactRIO terminal - everything works but if I try to call the script from my application using SytemExec VI - I get the echo output from my script and the error code is 0 but the virtual keyboard does not start. Seems like a trivial problem but I am stuck here...

Can someone explain to me what I've done wrong here and/or, maybe, suggest a better way of doing it, please?

in the LabVIEW environment one can easily execute a RT vi and if the FPGA bitfile is compiled it is automatically downloaded to the sbRIO target. It is very easy to stop the VI and quickly run a different one.

Without LabVIEW, one can from NI max, via the firmware update, change the code of the FPGA on the sbRIO, but it is much more time consuming.

What we would like is to have a couple of applications on the PC built with the LabVIEW application builder. The PC application should check if the required RT code and FPGA bitfile are already on the target, and if not, upload it and run it.

I do not know if there is a way to achieve that?

Any hints?

Thank you for your help.

I really need some help to kick off J1939 CAN interface development on NI-9853 FPGA.

There are some CANopen examples on the internet but nothing for J1939 and I don't even know where to start.

What makes life even more difficult is that the CAN module is residing on the Ethernet expansion chassis NI-9147.

If anyone could give me something to start with that would be absolutely fantastic.

Thank you in advance.

I would like to communicate via Phar Lab with a USB device that uses an FTDI chip. Is this easily possible?

Is there a RS232 to USB converter that can be used under Pharlab? A converter for a converter

I would be very grateful for any suggestions.

Greetings, Jim

I'm writing an Utility to retrieve image from Remote RT PXI system under PharLap 15 and RealTime 15. I use Create System Image.vi for that. During the execution this vi returns an error with code -2147220331 and description that some files on remote system might be corrupted. I desided to find out what is wrong with files and what are this files.

So I have "config3.mxs", "config3.mxs.jnl" and "RT" (with no extension).

What kind of problem is this?

I am currently involved in a project with a test sequencer based on actor framework executed on cRIO platform. One major problem that arose, is very long deploy times for the code to the cRIO. Meaning the start LabVIEW code in debug mode. It takes up to 8 minutes to get the code started.

I want to create a strategy on how to optmize the project to reduce the deploy times. And would be glad to receive some work experiances from the field.

We use LV2020. LVOOP is heavily used.
We do not use precompiled libraries yet. We heard from another company, that they had problems using it with actor framework, but cannot say what exactly was the problem. Are there any?

Thank you in advance.

Dermot

1. Copy the/one of the existing target item sections to a temporary file.

2. edit/replace the target header to define the right target type and hardware, an example is highlighted in the image below:

(If you do not know the correct DeviceCode (7740 in the case of 9063) and CCSymbol-values for the new target you can always figure it out by adding an empty target of that type to the project first...the device codes are also listed in your firmware folder and on the web.)

3. Then replace all instances of the reference to that target name with the new one in the rest of the spec, here the cRIO-9063 part would be replaced with cRIO-9030 if that is the name of the new target we need:

4. Now add the new item to the original project file and save.

A possible next step would be to write a little VI that does this automatically for you, you could make it recreate the build spec of a given target for a whole bunch of targets automatically....I have not done that yet. So far I am happy saving lots of time this way already 😀

I have not discovered any pitfalls yet, but perhaps there are(?) The applications build and run fine on each target... 

In my case all the target build specs are/can be identical (in some cases I might need to change a conditional disable symbol here and there though), but if yours are not then you can still use this shortcut to do parts of the job.

This screenshot is taken from here.

Is this code really more efficient? Does the Read Region block with high CPU usage like the Read FIFO method does? (I don't want that)

Has anyone used this "new" technique successfully?

For reference this is my current technique:

I have tried mass compiling and often that just crashes, but I did manage to get this log message:

Search failed to find "NI_Real-Time Target Support.lvlib:RT Get CPU Loads.vi" previously from "<vilib>:\Utility\RT Get CPU Loads.vi"  +=+   Caller: "System Status Actor.lvclass:Update.vi"

Now, this library does not exist at that directory, rather there is another vi.lib in Targets\NI\RT and it lives in that vi.lib directory

Now I am kinda stuck... My code runs sort of ok. Sometimes it just refuses to run on the cRIO (but I have seen this behaviour with RT for years now so just gotten used to it) but I cannot mass compile it or it just crashes. I have tried resetting the class mutation history but his also crashes LabVIEW 😞

Any ideas what I can try? This is a real pain. I do of-course have my history in git, but I don't really feel like trying to step back in time and figuring out what the heck actually happened.

Here's an example.  I have a Windows Main.vi, and a RT Main.vi both under their appropriate targets.  If I open the Windows Main.vi it opens relatively quickly, and loads about 2000 VIs and shows the main.  But if I then open the RT Main.vi, it goes through and compiles about 200 of those VIs taking several minutes to open.  So after both are open I perform a Save All, thinking whatever it needed to compile and do it should be done with.  If I then close the project and re open it, and then open the Windows Main.vi it has to recompiles those 200 VIs presumably for the new target, and then if I open the RT Main it has to recompile those 200 VIs again.  Is this how it is supposed to be? Every time I reopen a VI on a new target am I supposed to see it recompile for that target back and forth depending on where it was opened last?

The project has a mix of VIs that have separate compiled code on and some with it off.  Not sure which is better for this.

My computer is relatively powerful, but lately doing LabVIEW development makes me feel like I'm using a 10 year old PC.  Everything about my computer seems fast except LabVIEW development.  Is there tips or tricks, or options I should be using to help make my LabVIEW development more responsive, and require less recompiling when switching targets?

EDIT:  It seems that the VIs that need to recompile all the time are VIs that are in a Polymorphic VI, so the majority of them are reuse and OpenG VIs.

Double Edit:  It seems this thread from an older post on LAVA claims that the compiled cache has separate entries for a VI on multiple targets, so I'm not sure why these VIs need to recompile every time...

I have a linux based cRIO and have two problems, surely related:

1. I want a VI to show its FP when called (just using the tick boxes in the SubVI Node Setup config)
2. I want to be able to programmatically show and hide front panel windows. I pass a message to one of my running VIs and tell it to open the FP Window

Neither of these seem to work. In (1) the SubVI is definitely running it just does not show the FP window and (2) the method to open the FP window executes and there is no error in the code but nothing visibly changes

Now, this is not the kind of thing I have done in the past with a cRIO as I am used to running them headless.

Note: I do not actually have a display plugged into the cRIO, I was expecting the windows to open on my dev PC. Is this the mistake I am making?

Note2: if I move all this code out of the RT platform to the My Computer bit everything works perfectly as expected.

Note3: I probably should have mentioned this, the VI I am trying to control is a preallocated re-entrant clone. If I change it to non-reentrant then (1) works correctly but not (2)

I am running a real-time LabVIEW application that calls into compiled .so file. I am getting occasional crashes of the entire system, and the error log shows a segfault

#Date: Mon, Jun 29, 2020 04:59:16 PM
#Desc: LabVIEW caught fatal signal
18.0.1 - Received SIGSEGV
Reason: address not mapped to object
Attempt to reference address: 0x0x4
#RCS: unspecified
#OSName: Linux
#OSVers: 4.9.47-rt37-ni-6.1.0f0
#OSBuild: 264495
#AppName: lvrt
#Version: 18.0.1
#AppKind: AppLib
#AppModDate:

am I correct in blaming this on the code in the compiled .so file (which happens to be a ZeroMQ library) ? There really isn't a way for LabVIEW code to create a segfault AFAIK-- you don't have direct access to memory.

Also posted on the darkside but not expecting any response there.

Thanks in advance.

Strangely, NI do have a way to get this info as it is reported in MAX

Does anyone have a solution for this?

The interface of caraya generated by the test suite appears only if the test program is running on my computer.

if I run the test code in a PXI RT Target, the interface will not show up

Is there any solution to make it appears on my computer.

Thank you

choose files... Click to choose files

Thank you for your help.

in the current description of the NI Vision Acquisition Software it says:

http://www.ni.com/pdf/manuals/375130k.html

Deprecated Features
◾NI - IMAQ 19.0
....
◾Removed support for LabVIEW Real-Time targets running Phar Lap ETS OS

Will the OS Labview Real Time (Phar Lap ETS OS) be discontinued and is there an alternative based on Linux?

a good time

Jim

i want to low status 25ns is high status but hi2 case can't achieve, please help me

thanks you

How to recompile an image that can run on ZYNQ according to the LINUX RT source code on GITHUB?
The links are as follows:
Https://github.com/ni/nilrt/tree/nilrt/15.0

We are trying to connect a third party EtherCAT slave device to our cRIO 9039, which is configured as an etherCAT master. Problems arise when we try to activate the scan engine of the cRIO. The following error message appears: (see attached). Therefore the scan engine is pretty much stuck in its 'Init'  state and the cRIO is unable to communicate I/O data. We have been able to resolve the issue by replacing the cRIO 9039 with a Beckhoff PLC, suggesting that the third party hardware and .XML file are not at fault.  

Other things we tried to solve the problem include: install the correct Labview version (2018 SP1), device drivers (NI RIO 18.5) and industrial communication EtherCAT package (18.5). Unfortunately this did not resolve the issue.

All suggestions are much appreciated! 😄  

I have recently hit a peculiar issue when I was deploying a source distribution (SD) on a PXI Target running PharLap. The source of SD contained vis from NI's httpClient library,  so the SD itself contained (among many others) two files Get Lib.vi and GET.vi in one folder. 
Upon attempt to upload the SD to target via FTP, I have seen no errors no warnings, but trying to dynamically launch a file from SD that used httpClient resulted in thread stack overflow.  

By close inspection I have found out that I miss GET.vi file on the target. Moreover I was unable to upload this file by FTP.

Then I run code from snippet on the target can see Error 10 (duplicate path) appearing each time I want to create a file which name part matches "part before a spacebar" of existing file.

This  "feature" prevents me from using httpclient library on RT target, that I am heavily dependent upon.

Is there a way to overcome this problem ?

I'm trying to make a data acquisition and logging application for a PXI-8133 with PXI-4300 analog voltage input module, using shared variable single process with RT-FIFO enabled, but I'm having some issues with that.

I'm using a determinist loop for data aquisition and other while loop for logging. But, my log file is losing data, sometimes part of the signal is lost, sometimes the buffer is larger than the amount of data and saves a sequence of zeros. I'm having difficulty adjusting the values for the fifo buffer.

Here are some questions:
1- Should I use single element or multi-element at FIFO type? I believe a multi-element allows me to have a buffer, right?
2.1- Points per waveform in RF-FIFO settings should be exactly equal to the size of the waveform read in each execution of the timed loop or can it be larger?
2.2- The number points in the waveform read in the timed loop keeps oscillating, depending on the sampling rate. Is it normal?
4- Should the logging loop run faster than the timed loop or at the same rate?

Thank-you !!

at the moment I am working at a Projekt where I have to transfer much Data via TCP/IP and handle them via RT-FIFO´s .

So far so good.

But I had a lot of Problems with the cRIO TCP functions. If I send to much Data, Data gets lost or Fifo References got lost.

Maybe the cRIO TCP Buffer runs into a overflow...

Does anyone here have any experince with this behaviours ?? I am stumped...

System : cRIO 9014

RT Software : NI RIO 3.2.0

LabVIEW 8.6.1

To simplify the issues I'm seeing I created a class that internally just increments an integer every 500ms. The client asks the server what's the current count, the server asks the Counter class and returns the answer to the client. This works perfectly fine when running the VI in the IDE. When built it connects, will get the JSON message back, but always gets a default value from the DVR call (zero, in this case). As soon as I open a remote debug panel to the cRIO, everything is working. The count is correct, the client calls work, just like normal. As soon as I right-click, close debug, it goes back to zero. Open debug works, close debug, back to zero. I know the DVR isn't getting dropped because the count continues to increment while not in debug, the process is still running happily with no issues.

Here's a few screenshots of the code;

Count Class process (get the count, increment, write it back to the DVR) - Counter Class process

You can see the DVR vi's are actually vim's using a cast. I can't imagine that's the issue.

Server Side call - Server Side calls

All this does is get the count from the DVR (same as above) and wraps it in JSON and passes it back to the client as a JSON string.

I also implemented an Echo class that ignores the process and DVR's, it just takes whatever string you sent form the client to the server and passes it back with a prepended "@echo". This works when running as an executable with the debug turned off so I know the client, server, and the server/class calls are all working as expected.

Any thoughts here would be welcome, thanks.

edit: I added the any possible errors coming from the variant cast to the JSON reply. When the debug is open there are no errors, when the debugger is closed it throws error 91, but the in-place element structure reading the DVR does not throw any errors. How can a variant not exist until a debugger is opened and than it magically exists?

edit: the internal data dictionary is a wrapper around a variant attribute, I wired out the "found?" terminal all the way out to the JSON reply and if the debugger is open the attribute is found, but not if the debugger is closed. Anyone have issues with Variant Attributes in Real-Time?

Currently working on VeriStand custom devices, I'm facing a 'huge' problem when debugging the code I make for the Linux RT Target. The console is not availbale on such targets, and I do not want to fall back to the serial port and Hyperterminal-like programs (damn we are in the 21st century !! )...

Several years ago (2014 if I remember well) I posted an request on the Idea Exchange forum on NI's website to get back the console on Linux targets. NI agreed with the idea and it is 'in development' since then. Seems to be so hard to do that it takes years to have this simple feature back to life.

On my side I developped a web-based console : HTML page displaying strings received through a WebSocket link. Pretty easy and fast, but the integration effort (start server, close server, handle push requests, ...)must be done for each single code I create for such targets.

Do you have any good tricks to debug your code running on a Linux target ?

It does look like PROFIBUS DP uses an RS-485 physical layer which is good. Theoretically I could just communicate to the device with my built in RS-485 port. However, I am not finding any PROFIBUS libraries available for download that work with a generic serial port. I believe the NI-PROFINET driver is tightly integrated to the cRIO profinet module. I am also not jazzed about implementing a PROFIBUS protocol from scratch.

Does anyone have suggestions on good 3rd party adaptors or libraries that would allow me to communicate to this PROFIBUS device with a minimum of programming?

Recently I came across one issue, that I solved within a couple of minutes in Simulink, but cannot crack for a couple of days in LabVIEW. It is a Rising integrator (model and plots from Simulink attached). Mod is the modulus function (i.e. remainder), the integrator reset is triggered by the external “Trigger” signal at 1 sec. After that, as you see the integrator generates a ramp signal.

I was trying to represent the same behavior in FPGA LabVIEW in order to use it further on my cRIO. I’ve seen on the forum, that one of the most feasible solutions for the Quotient & Remainder function (i.e., Modulus in Simulink) is the use of a while loop system with subtraction. But the behavior of the system is different since it generates a ramp signal after the reset is on, but it has a negative slope and saturates at -37k.

Just to check in general how the approach works in LabVIEW, I’ve designed the second model with a Quotient & Remainder block (I know that for FPGA it is not the best option, plus I could not figure but how to use it with FXP values). But this model generates the output with a value of 5. Which is even more questionable.

In this case, could you please advise what I am doing wrong with the FPGA code for the block? Since FPGA is the main reason, why I am looking for any options but not to use the Quotient & Remainder block. Thank you in advance.

P.S. The models are designed in LabVIEW 2014 SP1.

Integrator_SGL.vi

Integrator_while_loop.vi

The crio system recognizes the USB-6366 as a USB RAW device.  So the question is it possible to control the USB-6366 using RAW communication?  I've got no experience in this area and haven't been able to find any documentation on this.  The application is pretty simple, just wait for a trigger, store some analog data, then download it to the crio for processing.

Ultimately the correct solution is probably to buy a couple NI-9775 modules, but for bureaucratic reasons this isn't possible now.

I am pretty sure this has something to do with Scan mode on the FPGA or shared variables or user-defined variables, however I am not very familiar with any of these.

Any ideas? 

Edit: the C-Series module that this node refers to is currently tucked away under my FPGA Target, so perhaps this is old test code from when the module was used in Scan mode? If I move the modue out from the FPGA to just under the chassis the little glyph looks different, like a  little blue square wave with a triangular wave just about it.

In max, there's a tool: "Creating Desktop PC Utility USB Drive".

I downloaded the files from NI website

and created an *.iso from the "image" folder.

However i wasn't able to boot that iso from VirtualBox.

Sorry that its off topic, just to check if anyone has the same experience.

I'm running LV2011, VB 4.1.4

Or, anyone has solution for this??

Many thanks!

I abandoned that approach in subsequent projects because it seemed not quite right. You have shared variables, why was I bypassing that entire system, which has a lot of functionality and add ons, for some parallel system ?

For projects where I just use the cRIO scan engine, I want to cook up a system where my test panel programmatically takes control of all the cRIOs's I/O via this "force variable" functionality. I'd like to run my the real time program on an cRIO chassis devoid of modules so I can see how the program performs on the actual hardware while testing out logic and functionality thorough manual test panels as well as unit tests.

Anyone one else do it this way or try it before?

I guess this boils down to two questions. 

1. Will the overhead associated with the matscript node for even the simplest script be high enough to utilize the entire CPU at a low rate like 1 kHz?

2. Can I/O be updated at 10-20 KHz through the FPGA I/O read write node?

Regards,

MarkCG

What's the best way to modify these two so they're better citizens of LVRT (i.e. no memory copies, or as few as absolutely possible)?

Query Command.vi

Real 64 Converter.vi

I am currently working on a project that is deployed on cRIO 9030 with NI Linux RT. My host user interface however does not look like the one deployed on the embedded one. Can you please share with me your experience on which fonts and sizes should I use to make it look as neat as possible ?  Maybe there exists a way to install additional fonts to the RT ?

For the moment I have just found this topic on NI community site : https://decibel.ni.com/content/groups/ni-linux-real-time?view=discussions#/?filter=answered&page=2

however it wasn't very helpful for me.

I would like to underline that I am a new member in our society, so if I break any of your rules or commons please feel free to point it out

I am quite familiar with different design pattern on LabVIEW but I am a newbie on FPGA design. I start working on a project for my own hobby using myRIO to control motor speed with PWM and read back encoder. This is the first part of my project and I plan to expand more later. This project will help me to get use to FPGA too. I am trying to learn a good design pattern by follow the template project which is "LabVIEW FPGA control on Compact RIO". In this template project, feedback value and control signal are analog channels and they connect directly with PID module in FPGA in a normal while loop. The configuration are sent from host. In my prototype project, I already built FPGA module to drive PWM and read encoder using single-cycle time loop. I plan to use PID in real time code. If I want to follow the template design, I have to change the way I implement the code for FPGA and Real-Time. So right now, I am not sure what is a good design I should follow. If you have any advice, I will highly appreciate. 

Thank you very much!

{F4C5E96F-7410-48A5-BB87-3559BC9B167F}

Does anybody know of a way to deduce the VI Server object type from this GUID so I can perform a downcast on it?

Before I get too deep I have to ask the most important question. Is this useful. So has anyone out there needed Database support on RT? Ideally there would be information about every topic you could come up with, but the reality is that if no one needs it I am going to use my time on something else.

OK assuming someone needs it, there are three scenarios I am pretty sure I am going to talk about.

1) The current NI recommended way to have databases on RT Targets is to make a communication layer between your RT and Host. Then have the host do all the real database operations, and the RT is just passing the information along. I have an example that has the RT send data over TCP to be recorded to a blank .mdb using the Database Connectivity toolkit. Then after some time the RT target requests something like 100 records to use in decision for state machine. Pretty straight forward, and shows that an SQL statement can be passed from RT to host without any translation of data on the host-side (in otherwords the host does not need to know anything about the data, it just works with variants).

2) The RT target makes files in a specific format, then the host retrieves the files periodically and places the data into the database. Some FTP operations, and thats about it. The file format is tricky, so I am still deciding on what to make it.

3) The coolest one by far, make RT targets actually support databases by porting SQLite to Pharlap and VxWorks targets. There has been some talks about it but I didn't see anything definitive on OpenG. Currently trying to get SQLite to build as a DLL in CVI.

SO:

A) Anybody actually going to use this stuff, or am I wasting time.

B) Does the three above meet pretty much all the scenerios you can think of?

C) Anyone been working on the SQLite thing lately?

I am working on Active Noise Cancellation project. I need to implement fixed point LMS code on FPGA target of myRIO 1900. I know , I can generate this using FPGA Target > IP Generator. I could do that, but I have to modify that code a litlle bit, as I will directly get the error e signal from microphone and there is no desired signal davailable.

I did some decoding and understood a bit of how it is working, but still could not understand some essential part of it! 

Below I will attach, the FXP LMS vi . There are also two subVIs needed which I cannot include here but I can add pictures of it if needed.

I could not understand, how this algorithm performs the Estimated signal step viz. [ y(n) = x_temp(n) vector * w(n) vector '  ; ]. I marked the section of the code where I am facing some problem in the attached picture. The algorithm does not show any clue how it is performing these vector operations.

I could not also understand, some logic with numbers that he has chosen like 8, 3 ,7 ,9 etc. 

Further clarifications on my understanding will be provided .

Any help in this problem will be appreciated.

PS: I could implement using memory blocks as basic array elements, like intialzing both x and w vectors. But eventually, I have to read and write several times, which is killing time.

FXP LMS.vi

My company has been developing and maintaining its own SCADA software in LabVIEW for a few years. It is fairly comprehensive: datalogging, graphing, alarm monitoring, automation, loops for equations and PIDs, and so on. It is a PC-based solution and communicates with many different kinds of hardware through the COM(RS232), USB, and Ethernet ports of the PC. This solution works well and allows keeping the costs low for most of our customers. Most of the loops run around 10Hz (100ms).

However, more and more we are running into customer specifications that require high control rate (few milliseconds), high determinism (to the millisecond), and high reliability. Not surprisingly, the PC solution becomes unacceptable. We feel it is time to look into a real-time, embedded solution for those customers. That's why I'm currently investigating the different NI embedded RT solutions (namely PXI and cRIO).

I can find plenty of resources on each of them, but close to nothing when it comes to comparing the 2 solutions and choosing which one to go with. Would you mind giving me some guidance? I guess you'll need more information, which I'll be happy to provide.

A few elements already:

- There is no request for MHz loops, so the FPGA side of the cRIO is not required I believe

- Our application contains many VIs that are both the engine and the HMI, so there will be some decoupling effort if we need to split it into an HMI application on the PC and an RT application on the cRIO. Would a PXI solution avoid this issue by plugging a monitor directly to the display port of the controller? But then if I have all the code in the PXI controller, is it likely that I will lose my control rate and determinism?

Thanks!

Emmanuel

I have a cRIO capable of rendering an embedded UI (cRIO 9039). Is it possible to Control that embedded UI by using VNC? Has anyone attempted anything like this?

Thanks,

Robert

Experiment with VI Property Node Error.zip

Currently, I have a .lvlib with virtual folders for RT and FPGA stuff. I have a few issues with this approach like requirement for changing FPGA typedef when I want to use it within another project and manual adding FIFO to the project.

Well, I can live with this, but maybe you have a better approach which you woluld like to share. I have found something like FPGA Advanced Session Resources https://decibel.ni.com/content/docs/DOC-35574 , but still I am not sure whether it something I am looking for.

Any thoughts?

Test Access to Shared Variable from cRIO.zip

I have faced the chalenge with setting values and synchronising measurement using multiple number of instruments. I use cRIO. The orginal application is a bigger but I will try to describe the main issue and my approach. I would like to listen to your feedback or better solution.

Let's imagine:

- device A (comunication over CANOpen) controlling speed.

- device B (communication over RS232) controlling temperature

- device C (NI analog inputs module)

The goal is to generate sequence of setpoints for temperature and speed and at the same time measuring current speed, temperature (using the same instruments) and measuring voltages using analog inputs.

Setpoint for speed should be generated quite quickly (it depends on perspective what means 'quickly' but period is 10ms), setpoints for temperature can be generated slower (period 100ms or bigger).

I can't wait for response from device B while I want to generate setpoints for device A (which is faster) so I decicde that I will divide these proceses.

My solution:

I placed device A controller into Timed Loop where it does three operations in sequence: writes setpoint, read current value and gets command from queue ( Timeout is 0 so I am not waiting for element and it is used only to stop a loop or perform initialisation - non deterministic tasks). The device B is in a similar loop but have different time rate. I wanted to keep instruments and logic separate so I added a third 'Control' Timed Loop which is responsible for generation setpoints at higer rates (1ms). The third loop 'publish' setpoints to other loops using 'single process variable with one element fifo' (one variable per setpoint) - in this way processes doesn't have to wait. All Timed Loops are grouped and starts at the same time. Now, it is time for FPGA. In order to have every mearuement correlated ( corresponding to each other), values measured by instruments are sent to FPGA. On FPGA I acquire values measured by instruments along with analog inputs and send back to the host using FIFO. I am receiving these values in non derministic acquisition loop. Control loop is also responsible for triggering the acquisition.

The problem seems to be common but described solution is the only one which I found to be correct and seems to be quite complicated (number of communication methods). Well, I hope I will get some advices to simplify it.

it is possible to synchronize the distributet clock from a PXI RT (Phar Lap ETS) EtherCAT Master with a third party slave (Beckhoff EL6692 or el6695 http://www.beckhoff.de/default.asp?ethercat/el6695.htm)?

Thanks in advance, Jim
 

I am trying to launch a vi dynamically inside RT. But I am unable to do it. It either throws up error 100 (VI not in compatible state for this operation) or just I get disconnected from the RT. I am not sure about the problem and I need help in this. How do I launch a VI dynamically inside RT. All its dependencies are downloaded to RT.

The VIs I am trying to launch is a member of a class. 

VIs property is set to be modal. (I want it to be front most when it gets launcheed. We are using LabVIEW Embedded UI for monitoring purposes). 

I am able to get the reference of the VI porperly. The error occurs in invoke node which tries to run the VI. 

Should the VI be reentrant for launching(a hunch of my own-but not sure why it should be)?

Thanks in advance for your replies.

"some of the compilation steps were not executed. refer to the Xilinx logâ€

The xilinx log is what looks like hundreds of pages. I see many warnings, but nothing that looks like a critical failure.

If I replace the sine wave with the square wave function, the code will run fine. 

I am running a cRIO-9067, with an NI-9269 module.

All I am looking for is a simple output sine wave VI. Freq and amp variable going in, and a waveform out of the RIO. 

Any help would be greatly appreciated. 

I have been using NI's examples (http://www.ni.com/white-paper/3780/en/#Example, fig2) linking to my hardware.

I suppose I'm looking for a few answers here:

1. Why does this fail compilation? 

2. Does anyone have a VI that will just simply output a sine wave?

Thanks again,

Chris

However I want my RT app to be stand alone and adapt to different chains of slaves.  When I invoke the Refresh Modules method it finds all the available slaves including the buggy ones.  These then prevent the Scan Engine from switching to Active mode.  I have not been able to find a way to programmatically remove these buggy slaves as I can from the project - does it exist???

Many thanks!

When I try to establish a connection using my Windows 7 PC as the client and my sbRIO (VxWorks) as the server, it connects and pushes 100 messages from the client if the server was listening first. If the client spins up first, sometimes it works and sometimes I get error 56 from the "TCP Open Connection" primitive repeatedly. Other times I've seen error 66.

When I try to make Windows act as the server, the sbRIO client connects without error, but it returns error 56 from "TCP Read" on the first call thereafter (inside "STM.lvlib:Read Meta Data (TCP Clst).vi"). This happens in whichever order I run them.

This test, and all others I've written for the API, works just fine when both client and server are on the local machine.

-------------------------------

I'm tearing my hair out trying to get a reliable connection-establishment routine going. What don't I know? What am I missing? Is there a "standard" way to code the server and client so they'll establish a connection reliably between an RT and a non-RT peer?

I'm planning to make a 3-floor miniature elevator (this is the prototype) and it will be controlled through LabVIEW. The LabVIEW interface will control what floor will it go up and down. But I have (super) major problems. First, which one is better to use for the interaction of prototype and labview, DAQ or Arduino? Next is that I don't have that much idea how to start the VI. I've seen some elevator VIs but I think I must read or research more. Also, is there a transfer function involved in the VI? 

All help will be greatly appreciated. Thank you.

I would like to do some moving averaging on my FPGA based on building the sum of the values to around 200/N data points and then removing the oldest value and adding the newest value that way I'm only needing to acquiring one new point once the data point have reached the 200 limit but I have 16 channels and FPGA does not support 2-D arrays and I can do it with 16 1-d arrays but I don't think there will be enough resources on the FPGA. Anyone have any ideas how i can do this.

I guess the main challenge is having a way to continuously store the last 200 or N points so that I can subtract the oldest value other than a two d array or multiple 1-d arrays. I am trying to do it this way as well so that I don't need to wait each time and acquire 200 or N samples and then averages them each time for a new averaged value.

Kindly let me know if any suggestion.

Thanks in advance.

Pravin

I'm designing RS232  using pxie-8100 RT.

is the rs232 design and configuration is different between Labview RT and regular Labview ?

cause the same rs232 design doesn't work on the RT labview...

I have implemented first order filter in Real Time and trying to implement in FPGA.

Please attached code for your reference.

The code below tests using the Matrix Multiply function vs just straight array math.  Unsurprisingly the Matrix Multiply function executed faster.  Then when I ran it on RT both methods took the same amount of time? And Matrix Multiply (A x B.vi) takes LONGER on RT than PC?  Is there some windows-optimized code under the hood that is not available on RT?

I was hoping it would be faster since my laptop is several years old and this is NI's super duper 8135 PXI controller. I did deploy this as a startup app to ensure running from the IDE did not affect timing when running on the RT.

I have an application where I need to sample at a specific higher rate to calculate RMS values and feed some of my values over FPGA front panel objects to a fast loop on my RT and send the samples at a slower rate (triggered by a timer) over a DMA FIFO to slower loop.

I Set the loop time to 10000 S/s and i'm filling up the DMA FIFO every 50 ms. The diagram looks something like this:

My question is: does the FPGA code execute the auto-indexed FOR-Loop like the Non-FPGA Diagram would, where the single Trigger bool from the timer remains true for all cycles of the for-loop, OR do I need to make sure the "Triggered" condition of the case structure is there for all FOR-Loop cycles? 

Thanks,

Robert

Here's the situation I'm working with.  There's an existing cRIO based software that needed a quick fix.  In order to do so and report back to the Windows host a Network Shared Variable was added.  This variable is updated during the initialization, but is polled during an idle state in the RT code main process.  The NSV is not wired with error wires (currently) in this idle state.  No buffering or RT FIFO is enabled.  I have an intermittent problem where the NSV in that idle case is claiming that a part of the initialization failed though it hasn't (it's sole purpose is to monitor this).  Here's the question:  Is it possible that the NSV in the downstream loop and case structure is being populated before the initialization completes?  It is my understanding that a structure will act similarly to a subvi in that *nothing* inside it will execute until all the inputs to the structure are available.  However, this is the only sane explanation I can come up with to describe this behavior. 

I would like to ask which method should I use for transferring latest data between determinism process. I don't want to use single process shared variable with RT FIFO enable since it will polling data. I don't want to use the RT FIFO function because I cannot send the latest value. Queue is not determinism. I am not sure if Notify is determinism or not. Anyone with experience about this?

Regards,

Thang Nguyen

I have a Windows app that talks to my RT app. In the interest of dividing labor, creating automatic unit/subsystem tests, allowing multiple devs to build on their own machines, etc. I need to be able to simulate the RT program on Windows.

So I abstracted all the calls to NI-RIO using Conditional Disable Structures and added a "Simulator" VI that wraps the entire application while hooking into some custom messages so it can display information to the user. When I need to run on Windows, the RIO calls don't execute and the Simulator panel ties into the network connections. When I need to run on RT, the Simulator panel isn't called and the RIO calls execute. It works great....except on machines that don't have the LVFPGA module installed (because they only develop the Windows app). Even though the ConDis structures prevent code from being called, it still gets statically linked into the app. This prevents a Windows-only system from building the Windows app: it throws errors while looking for FPGA Module components.

What's the best way to abstract the FPGA reference wire from the code to work around this? I hate the idea of creating a class hierarchy for my IO calls and dynamically loading the class at runtime because dynamically launched code is nearly impossible to debug on LVRT.

I discovered I really like being able to easily shift between RT/FPGA targets.  It makes development so much easier and faster compared to remoting in to a client's site.  My question is what are some good ways to manage code so it can run on multiple target types?

Currently I have two targets in my project, one sbRIO and one cRIO.  All the source code is listed under both targets.  It seems to work, but there's a lot of bookkeeping to track because many resources aren't shared between targets.  (FIFOs, registers, memory blocks, build specs, etc.)  It requires me to keep all the resource names synched and make sure the properties are identical.  I'm constantly worrying about screwing it up.  Is there a better way to do this?

I noticed the sbRIO-9636 uses the Spartan 6 LX45 and the 9074 uses the Spartan 3 with 2M gates.  I assume I cannot use the bitfile from one for the other?

I've been using conditional disable structures a bit and noticed there is a TARGET_CLASS symbol available when using it on an FPGA vi.  The help files don't give any information about that symbol.  Anyone know what it does?

I have several(6-10) concurrent tasks going in my RT code, most of them are idle however, sitting on a dequeue with a -1 for the timeout. My communication manager loop is waiting for a message from the PC, and when it does it will enqueue a message to on of the concurrent tasks. The task will do a little casting as needed, then start executing a task that can take anywhere from 5 sec to 5 min. Some of these tasks involve time critical sub components. None of the time critical parts run for longer than 30 seconds.

So as someone who's more experienced with desktop programming, all those dequeues look like 0% processor usage to me. And judging by the distributed system manager, the CRIO seems to agree. When there's nothing going on, my CPU usage drops down to the 15%-20% range. But I'm still getting weird softmotion errors (like -77055).

So my question is: Does a dequeue with a -1 timeout tie up the CPU in RT, even though the usage doesn't seem to show it?

I am looking for a way to verify all the USB devices have enumerated.  Polling VISA Find Resources appears to cause the entire system to lockup if we start it immediately in RT app.  If we manually delay for 10 minutes or so in the application and then call VISA Find Resources, it appears to work OK as long as all of the devices have successfully enumerated.  A hard-coded 10 minute delay is not optimal because on soft reboots, the delay is unnecessary.  

Are there any other ways to get the state of system USB enumeration other than VISA Find Resource?

During reboots, the NI boot loader takes a minute or so to "Enumerate USB devices" but it appears it only enumerates each USB hub before it completes and moves on.

PS. I know there are latency issues using USB on an RT system.  We chose to use the RT platform for stability (no windows updates, etc) vs determinism.  This may or may not be a good reason, but its what we have now.

The Variant to Flattened String prim crashes an RT application in LV13. Does anybody know another way to get the type descriptor of a cluster?

Got it using VIs from vi.libUtilityVariantDataTypeVariantType.lvlib

GetClusterInfo followed by a FOR loop with GetTypeInfo.

I'm just beginning to feel out what would be required to write a driver for a 3rd party PCI card in LVRT. The outline is thus:

I have a laser interferometer card from Agilent, there are no drivers that I'm aware of for pulling information from the card directly into the RT system. My lab has been using a custom built hardware interface which taps off the hardware-out lines on the card when it is installed in a windows box, and reads the lines into an FPGA card in the RT box.

This means we have to maintain two systems, a windows box to host the card, and an RT box where we're doing all our control. I'd like to simplify the system by doing whatever is necessary (driver?) to install the card direct into the LVRT box.

My initial google has turned up resources for Veristand (I'm not familiar with it at all, and assume it isn't what I want), and not much else.

The install disc I have provides an API (headers with function declarations and register maps) but doesn't expose the functions themselves (they're in a compiled dll I think) There is also a pretty comprehensive manual about the register layout. My RT operating system is Pharlap, which can apparently call functions from a .dll (linky). The driver is a .sys file, could it be as simple as ftp'ing this into the right place along with the .dll and using "Call Library Function"? I couldn't find any information about what type of driver file Pharlap (and LVRT) expect, but I suspect it's not .sys (too good to be true).

Anyway, I'm wondering if someone could point me in the right direction? Possibly with a link to any tuts/white papers about LVRT driver development?

Many thanks for your time!

Kind regards,

Alex

Obstacles:

The PC is not running any LabVIEW code, so no PC publishing time to network shared variable stuff

The code on the PC is legacy C# code that I cannot modify to include timestamp messaging between systems

The PC and attached RT PXI are network isolated, so no using a domain controller time service

My only solution to get the time from this generic windows PC (assume WinXP or newer) is to install an NTP time service on it that I can query via UDP from the RT application.  I have done this before, but it just feels unsatisfactory.

Anyone else solve this problem before?

     I have a problem with the crio-9073 and a stepper driver 9512, the status led starts flashing 4 times, that according to the manual is a memory usage issue, but I don't think that's the problem since I haven't run any program on it, It starts when following the tutorial to use hybrid mode, I have I/O cards under an fpga program and the stepper module (9512) in scan mode, when everything it's deploy and try to switch the target to active mode it says that the NI Softmotion didn't detect the module, I restart the target and then when loading the module (when the leds of the 9512 start to come up) the status led starts to flash 4 times.

     I format the crio, install all the software (NI rio, softmotion, fpga, picture attach) and do the same tutorial,

http://digital.ni.com/public.nsf/allkb/12287236ED86B789862576630059572C?OpenDocument

     and when the 9512 module leds start to pop up, the crio restarts and then the led status start to flash 4 times again.

     I don't know if I'm doing something wrong here, but I really need your help with this.

Thanks in Advance

Javier Rocha

1. RT controller properties in project

2. A front-panel control on a UI vi that connects to the RT controller

3. A constant in an RT Main vi to set the target for the FPGA BitFile

I'd prefer to make this more portable and more easily maintainable in this shared satting under VCS, ideally just popping up a panel that offers controllers to connect to so the operator just clicks on a system to connect to. Desired features would be:

1. Dynamically identifies connected cRIO controllers

2. Offers choice of controller to connect with

3. Remembers last choice with ini file and automatically connects if there is only 1 possible target

Thank you for any help.

Ryan Rutledge

     I have a newbie question, I want to create an app that controls a stepper motor and some I/Os, I have read documentation that said that a hybrid mode is the best way to do it, so I installed all the "necessary" software to do it and only left me with very little memory that my code won't run, my problem is that this is my fist with cRio and I don't know if I'm using the correct software, I have attach a screen shot of the software that I have installed on the target and another with the target information.

     I'm using Lv2013 and NI-RIO 13.0, FPGA module and the softmotion module as well, is there another way or some NI knowledgebase that I missing, any help will be appreciated.

     I don't know if I'm describing my problem correctly, so if you have any doubts please let me know, I just want to know if I can save more memory because I'm using the wrong package or if my code need to be more slim.

Thanks in Advance

1. Is Softmotion advisable to be used for motion control where the data rate can is upto 20KHz? Not sure if SoftMotion only works with scan engine and according to cRIO developer guide, for rates >500 Hz FPGA should be used and not scan engine. What are the limitations of using Softmotion?

2. In one application can FPGA be used to do I/O with one module and scan engine be used to do I/O with another module?

Just wondering how long does it take to develop a LV application with Softmotion if basic motion control is to be performed. Thanks.

i've a project on a cRIO with some I/Os running under LabVIEW 2012.

Now i want to visible my results on a website with the cRIO webserver. So i wrote a web service witch show the content of some shared variables.

Because the default website show only a table with each name and content of the variables, i toke a string variable and save a html link to a picture in it (<img src="myGraph.bmp">).

In my LabVIEW code i get the image of the graph using a property node and save it to an *.bmp file.

Code of the initalisation of the variable and saving an empty graph at start up:

Now when i deployed my program the picture was saved and the website look like i want to.

But when i run my cRIO as a standalone it seemd that he didn't open the frontpanel and so he take an empty picture with.

I checked if the frontpanel was removed by the build specifications and i try to set a invoke node to open the frontpanel first.

But both didn' help.

I'm a native html but a good LabVIEW programmer. So i try to solve it in LabVIEW.

But perhaps there is an easier way in html. But up to now i don't know how to reference to the webservice variables from an html file.

I found an example for forms connecting to webservices. There i've to send the returned website with a LabVIEW build html string and i don't know how drawing an graph in html.

Now i'm thinking about drawing my own graph in a picture with LabVIEW and saving them...

So have anyone an idea how i get a graph easier to the website?

thanks for help and sorry for my bad english grammar

Oliver

The primary use of Functional Globals is to provide data sharing across an entire project, both horizontally and vertically.

In the past, I have successfully used FGVs to share data among VIs running on the same target. In my current project, which involves multiple targets (namely, a host PC and a cRIO), I now want to pass configuration data between a Host VI and an RT VI, and I thought an FGV would come in handy for that.

However, it doesn't seem to work: I write to the FGV on the Host VI alright; but when I read data from the FGV in the RT VI, I only get default values, as if nothing had ever been written to the shift registers. Before you suggest it: yes, I have checked the VI properties of my FGV; its execution is set, as it should be, to non-reentrant.

Can Functional Global Variables be used to share data between VIs running on different targets? Or is an FGV's scope limited to the target it runs on?

Unfortunately, I couldn't find any answers to those questions in the LabVIEW online help, or on any LabVIEW discussion board...

recently i have come to a odd problem with lvrt(ets) and have no idea about how it goes. 

My project uses 10 or more dlls which were wrote by third party and had been put into the RT's C:ni-rtstartupdata  folder, and this path had been added to the system find path list. Each of the dlls may have several VI calls(each for different functions in the dll) in the project. And when i try to deploy the whole project, my RT hung with one of it's cpu went to 100% loads.

And the odd thing is, when i try to disable one of the dll (means to disable all the vis that call the dll through the "call library function node"), the deploy goes with no error and my application can run as expected except the disabled parts! During the past one week's struggling with this deploy problem, once i can come to a particular configuration (by removing some no use modules in the RT or changing the dll call's  from "run in UI thread" to "run in any thread"), and under this situation ,i can deploy my project to rt, but when i run, a exception string appears on the RT's screen, which says "flushing disk cache" and something like "system error".

Here i have two questions:

1,   does the ets os system have a max number of user defined dlls that can exist in memory at the same time?

2,   does anyone come to the "flushing disk cache" error before in the ets system? can you share some experience with me?

any suggestions are welcome and will be appreciated.     i am looking forward to your share, many thanks in advance!