Any help is appreciated.

Editing  to add:

Some information on only LabVIEW 2019 and older can be installed the old way

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000001DthyCAC&l=en-US

2020 and newer installation is done differently.  What I'm concerned is if all sbRIOs are supported with new method.   I'm guessing not

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000000x2jQCAQ&l=en-US

end of edit.

Note: I have tried to post this on the NI Discussion Forums but it is "under review"...

I am trying to get my FPGA program working. I have been able to get the first three modules working (at least not throwing an error when the FPGA starts I haven't actually tested data though put yet) but no matter what I do I can't get the 9213 to work except an empty example project. If I diagram disable the loop with the NI 9213 (Module 4) calls in it the FPGA will run with no errors.

Here is the error I keep getting :

Error -61017 occurred at Open FPGA VI Reference in NI 9213 Getting Started (Host)ud.vi
Possible reason(s):
LabVIEW FPGA: You must recompile the VI for the selected target.
=========================
LabVIEW FPGA: You must recompile the VI for the selected target.

Here is my setup: 
LabVIEW 2024 Q1
cRIO-9064 (Firmware: 24.0.04129, OS: NI Linux Real-Time ARMv7-A 4.14.146-rt67)
Slot 1, NI 9203
Slot 2, NI 9265
Slot 3, NI 9474
Slot 4, NI 9213

As a test I used the NI 9213 Getting Started.lvproj from the example finder to verify that the module by it self would work. And it does. 

To make the example work with my system;
* Create a copy of the example
* Right click the Project name -> Add Target and Devices
* Select Existing target or devices -> Discover an existing target(s) or devices(s) -> Real-Time CompactRIO -> Select my cRIO
* Click OK
* Select LabVIEW FPGA Interface
* Click Continue
* Click Discover
* Copy the NI 9213 Getting Started (Host).vi from the sample cRIO to my cRIO
* Copy the NI 9213 Getting Started (FPGA).vi from the sample cRIO/FPGA Target to my cRIO/FPGA Target 
* Create and Build a Build Specification for the NI 9213 Getting Started (FPGA).vi 
* Open the NI 9213 Getting Started (Host).vi and right click the Open FPGA VI Reference select Configure Open FPGA VI Reference
* Select the Build Specification created above
* Click OK 
* (optional) Add an probe on the Error wire between the Open FPGA VI Reference and the Reset (Invoke Method) 
* Click Run at the top

Next I added a second loop in the NI 9213 Getting Started (FPGA).vi and added in the channels for the other modules. It will compile just fine but as soon as I try to run it it, the Open FPGA VI Reference throws the above error... again (See the NI 9213 Getting Started (FPGA) - w other modules.vi, The top loop is the added modules and the bottom loop is the untouched loop from the example)

Next I disabled the new loop and recompile and it still throws the same error. You can see the diagram disable statement around the top loop. 

Next I deleted the new loop and recompile and it still throws the same error. (saved the NI 9213 Getting Started (FPGA).vi as a new vi so I could keep the previous one as a sample and created a new build specification)

Next, in the project I disconnected from the cRIO, changed it's IP address to 0.0.0.0 and re-added my cRIO again (same steps above to add my cRIO to the sample project). This time I added the re-named NI 9213 Getting Started (FPGA).vi to my FPGA and recompiled again, and it works. 

So a few comments / observations,
1. In the attached vi, in the bottom loop, the case structure that is connected to the error wire, I can't use that in the top loop. I tried to reproduce this in my original project and I had to use Error State boolean from the unbundle by name in both loops. This seems odd to me.
2. I am not worried about the timing right now. The only thing I really want the FPGA for is to create a PWM output from one of the DO channels. If I can't figure this out by Monday I am going to try to switch to Mixed Mode and put everything except the DO module on the Scan interface. 

I have done similar things to this in the past but I can't figure this out. 

Any help would be appreciated.

Thanks, Ryan

NI 9213 Getting Started.zip

Reading the data with a normal loop on the FPGA works as expected but the achieved speed is not very high.

I've tried to do the same by using a SCTL with a case structure where each case of the structure should not take more than a single tick to execute.

By looking with the oscilloscope the pulses generated and read seem to be OK.

The read conversion data seems, however, to be missing the MSB.

When reading for instance a voltage over the ADC range, I read 0011111111111111 instead of the expected 01111111111111111 (the ADC sends the data on two's complement).

I am missing something?

Any hints would be welcome!

After searching both forums I've not been able to source a way to easily create either file format. There are examples reading these files but not writing them.

Segger simply gave the Python script below.
Unfortunately we can't simply just install Python as this is in a regulated environment. So we're hoping for a native LabVIEW solution.

Surely someone has done this before. It gets a bit complicated if we need to roll our own down to the bit level & then having to do a full validation on it. I'd really rather not go there.

Thanks in advance!

python script (the "intelhex" does the heavy lifting)

from intelhex import IntelHex

h.write_hex_file('patch.hex')

I have device based on FPGA.

I'm trying to program using Labview over JTAG. 

How can I do it? Is there any library JTAG Labview?

Thank you!

I have to deal with IRIG B protocol on a compat RIO. It's a 9074 and the IRIG signal is wired on a 9402. I searched on the NI website and found 2 libraries that seems to decode IRIG :

• IRIG-B Implementation in LabVIEW FPGA
• FPGA Timekeeper

I played with the first one and succeed to get day of the year and hour, but not the year. 

As the second is recommended by NI to be used with 9467 and it is said to be compatible with IRIG protol ("The NI FPGA Timekeeper is LabVIEW FPGA IP designed to integrate the CompactRIO onboard field-programmable gate array (FPGA) clock with external timing sources such as SNTP, IRIG-B, and GPS."), I thought it would be a better solution.

My problem is that there is no example of the use of timekeeper with IRIG protocol and I don't know how to use it in this way. Does anyone has already use timekeeper with IRIG B protocol and can give me an example?

Thanks in advance

BR
Yann

I am trying to use image convolution inside FPGA. My Image size is around 6kx2k. The convolution is applied properly until 2600 pixels in x resolution. After that, the values seem to miss previous row data. 

In Detail: As convolution is matrix operation, image data needs to be stored for the operation. But it seems there is an inadvertent error storing only 2600 pixels per row inside FPGA. And hence the filtered output is calculated assuming these pixels to be 0. 

I have tried with different image sizes, different convolution kernels, and also in different targets (cRIO 9030 and IC 3173). All results are same.

I have attached a screenshot of FPGA VI and an example image.

The example image shows an input image of 4000x2500 of same pixel value 16.The kernel is 3x3 of values 1 with divider=1. The RT image is processed using IMAQ convolute inside RT controller and has value 144 [(9*16)/1] for all pixels. But the FPGA processed image (zoomed in) has 144 until 2597 pixels and then 112 (7*16- showing 1 column of 2 rows missing) at 2598, 80 (5*16- showing 2 columns of 2 rows missing) at 2599 and 48 after that (missing 3 columns of 2 rows- current row is always present). This shows the data is missing from the previous rows after 2600 index.

Is there some mistake in the code or any workaround available?

I would like to have the digital trigger high for user input time in seconds.

Any help is much appreciated. 

Data Acquisition Final.zip

If I generate an FPGA IP core from my LabVIEW code, can I use it somehow in traditional FPGA development environments, such as Vivado?

Thanks,

David

I’m not sure which forum is the right one which is why I created two new topics with the same content (one in Embedded and one in VI Scripting) – so sorry for the spamming.

I have two questions:

1. How can I generate a cRIO project programmatically?

2. How can I start the “Discovering Devices” tool of the Project Wizard automatically?

At first I will describe a bit more what I really want to do:

I’m about to write an auto coder which should create a complete new FPGA project on my cRIO system without any user input. In the Project Wizard I want to run the “System Setup” from NI standalone. In that mask the NI project need some input like project type which is always a cRIO Embedded System. The next step is to insert an IP address to discover an existing system.

As those two steps are every time with the same input, I want to give them those parameters so that everything runs automatically.

Is there anybody who can help?

Thanks a lot!!

The "one thing" is the Ascii to UTF16 conversion since the protocol uses unicode. With the older protocols (NTLMv1 etc) that is not an issue since the negotiation can tell the server to use ASCII strings instead of Unicode. However. NTLMv2 requires unicode strings to create the hash in the specifications so there is no negotiating it  away.

(Note: There is no need to display anything so the bytes just need converting for calculation from a LabVIEW string to a u8 byte array representing the unicode equivalent. No changes to LabVIEW indicators or ini-files is required)

Under windows, the conversion from ASCII to Unicode is via calls to the OS (kernel32.dll). So am I looking at iconv, mbsrtowcs or something else to achieve the same on Linux and Mac?

.

- PXIe-1082 chasis

- PXIe-7962R FlexRIO

- custom MRF timing card

I want to send data via the DStarB line from the custom FPGA to the FlexRIO. I am reading the DStarB line in my LV FPGA program.

The problem I have is that I only get the data when the DStarB line goes from '0' to '1'. If I send two '1' after another I only get the first one, because I only recognize the positive front. I would wager that the backplane has a setting for this DStar lines. Some pull-downs or something...

I cannot read the VI_ATTR_PXI_DSTAR_BUS and VI_ATTR_PXI_DSTAR_BUS_SET attributes of the PXIe-7962 card from the LabVIEW program. The attributes are also not present in the VISA Interactive control Attributes list.

Is there a problem, because the crate is not configured to work with my custom timing card?

Or is the problem in the FlexRIO configuration?

Do I need to enable something in the chassis settings in NI MAX? I went over everything but cannot find something useful.

Do I need to configure the backplane with my timing card somehow?

I am running out of ideas, so please do help.

When I try “my way†of implementing a simple FPGA Analog Out VI, I run out of FPGA fabric (too may LUTs used).

So what better way can I do this (if there is one), that don’t overuse my LUTs.

My task is to:

Make one analog measurement and control 2 analogue outputs that should be clocked out every time I get a digital trigger in.

I’m running a sbRIO-9637 (Zynq7020)

I’ve attached the simple application and I’m puzzled of what needs so many Look Up Tables (LUTs).

Any suggestions?

FPGATest.zip

Has anybody ever tried to customize the web based configuration interface for compactRIO ? My goal would be to « inject Â» some custom configuration code into the actual interface. For example I would like to add a new icon in the banner on the left edge of the page and display a form of my own in order to configure custom settings (see screenshot enclosed). Benefits of this feature would be great concerning user experience (only need a browser, single interface to configure a device, no need to develop a full custom LabVIEW configuration HMI using NI System Configuration API ...).

I'm not sure if this customization is possible, and I wonder how to achive it cleanly. Maybe NI provides an overload mechanism like using hooks or something comparable ?

If somebody has informations or experience about this topic, I’m highly interested in.

Thanks for your help,

Nicolas

Best I could find via google is this idea exchange posting that describes a perceived defect in this area (change in IP address of NI Real-Time Hardware Target - and am going to investigate if this is the root cause of the experienced issues):

http://forums.ni.com/t5/LabVIEW-Idea-Exchange/Enabling-use-Labview-FPGA-front-panel-in-interactive-mode/idi-p/2012956

As asked in the above link, is this different IP issue a defect? Any insights or experiences to share regarding this described situation?

I've cross posted this to ni forum as well, to increase exposure.

Thanks for your time - Chris

http://forums.ni.com/t5/LabVIEW/FPGA-interactive-mode-in-multiple-develeloper-environments/td-p/3184841

I'm using a compactRIO and need to update the internal time of the device to be clock synchronized with my whole system. Everything seemed to work perfectly but when I try to apply an offset between 0 and -30 seconds, my compactRIO freeze. Nothing happen if I apply a positive offset or an offset "higher" (in a negative way) than -30 sec.

The duration of the freeze equals the offset I apply on my device and after this delay, everything comes back to normal. The freeze affects all my RT code (other processus as well) and not only the VI where I use the "Set Time.vi". The FPGA seems to be working during the freeze time because I got "DMA is full" error after the freeze and some LEDs keep blinking during the whole time.

Has any of you already noted something similar on compactRIO 9068 (Linux) ? Or do you have any idea of what is going on ?

Thanks for you help.

Nicolas

Additionnal informations :

   - LabVIEW 2013 SP1

   - NI RIO 14.0.1

   - CompactRIO 9068

   - Linux Embedded

   - LavBIEW Real-Time 13.0.1

I am trying to have an OOP based architecture inside RT ,where FPGA acquired values are used inside RT. So my plan is to have a generic base class upon which different systems(Child classes) are built. My child FPGA VIs will have additional controls in Front panel along with the common ones. So where can I put the FPGA ref? I cannot have it in base class since it will not bind all the controls. But if I have it in Child classes, how can I have the common functions in Base class?

Looking forward to your suggestions guys..

I am trying to compile an FPGA code which results in the error as follows:

ERROR:HDLCompiler:1566 - "C:\NIFPGA\jobs\t1y1Y1O_hxEgG35\NiFpgaAG_0000002b_SequenceFrame.vhd" Line 42: Expression has 32 elements ; formal ceioparameter0signal expects 24

How do I debug this. I have no idea about how xilinx compilation. Help me 

Thanks,

Prabhu

The integral and derivative actions of PID do not seem to track equations shown in documentation.

Derivative – PV set using triangle wave 0 – 10 – 0 at approx. 1 Hz the derivative of PV should alternate between +20 v/s and -20 v/s. The PID output maxes out at +/- 1 when Kd is set to 128. (Kp = Ki = 0.) Based on documentation the PID output should be +/- 20 when Kd = 1, and then 20*128 = 2560 when Kd = 128. Not sure why the effective gain is so small.

Integral – The error is set by setting SP = constant = 10, and varying PV using triangle signal noted above. The error is then a triangle that varies from +10 to 0, again over ½ second. The integral, therefore, should be varying from +2.50 to -2.50 over the complete cycle.

 Issue 1: The integral effect on PID output does not change sign when error integral goes negative. It appears that there is some absolute value function that only allows positive integral action regardless of error integration.  Likewise, if Ki is set to negative number the integral PID action only goes in negative direction. This implies that as the PV crosses over the SP level the integral action will keep adding to PID output that will then drive PV further past SP.

Issue 2: Unlike the derivative effective small gain, the effective integral gain is very large. With the Ki set to the smallest number available using FP 16.8, (approx. .0039). the PID output varies from 0 – 12.5 with the actual integral varying from -2.5 to +2.5. Not sure why the effective gain is so large.

I am presently using the kinect Face Tracking Basics WPF c# program to track a manikin head and extract z-coordinates which represent the distance of the camera from the manikin head. At present, I am writing this coordinates to memory using the memorystream method in c#.

The problem is I want to send the z-coordinates to the fpga on myRIO using the Host to Target scope in the link above. So far, I can't figure out how to do that. 

Is it even possible for labview to access physical memory on my windows computer?

I look forward to your replies.

Thank you!

DMA FIFO Code.zip

Is there anything similar to "DMA MEMORY" that behaves like DMA FIFO, but without the FIFO part?

I would like to transfer 1000 bytes of data from the FPGA to the cRIO host and 1000 bytes of data from the host to the FPGA and I don't care about old data - I only need the latest data.
Ideally I would like to have two pieces of memory, each 1000 bytes long.
One piece that can be written from the FPGA and read from the host and the other piece that can be written by the host and read by the FPGA, so that the first byte of data is always on the address 0.

DMA FIFO is not a viable solution, because I would like to get the data as fast as possible, but I can read it on the host only on certain non deterministic intervals.
If I would use the DMA FIFO, I would need a huge FIFO to store all the unused old measurements.

Thank you for any reply or suggestion.

Kind regards,

Greg
 

Has anyone else had a problem like this / know how to fix it? Thanks.

Never mind; I managed to get it to work eventually. In case anyone else has this problem, I simply had to install the software through MAX, by opening "Remote Systems", expanding the "NI-sbRIO9636-xxxxxxxx" item, right-clicking Software, and selecting "Add/Remove Software".

However, one thing I'm curious about is how I can directly access the file system on the board. I assume standard file I/O nodes in an RT VI will do it? I'd still like to have a regular file manager, or maybe an SFTP server.

Figured that out too! It's in one of the web configuration addons you can install from MAX.

But one question remains: Is there a shell of some kind I can connect to?

I am currently having some issues with a FPGA program with Softmotion not compiling.

We are running out of options in terms of how to get this FPGA program compiled.

So my question is does compiling on Linux have a different probability of compiling FPGAs?

I have heard that Xilinx Compiler is meant for Linux so it runs more efficiently and faster,

so I was just wondering if the compile method was different as well

Also, with that driver, would I be able to program a Digilent BASYS Spartan 3E board? I'd like an answer quickly, because I found one on eBay that's Buy It Now, but I'm afraid someone will bid before I know it'll work.

Long time reader, first time writer.

I'm currently trying to develop a data gathering system using a NI sbRIO-9606.

The premise is quite straight-forward; I have a digital signal (data and clock) with a bitrate of 10 Mbit/s which I want to store to a USB flash drive in real time. The single-board RIO has no problem reading and processing the bitstream but storing the data to the USB flash drive is apparently not as easy as I thought.

According to the manual the USB port supports a transfer speed up to 480 Mbit/s (USB 2.0 standard?) but I've been unable to achieve any faster transfer speed than around 1 Mbit/s (1.3 Mbit/s worst-case). This is unaccaptable for my application!

I'v tried to disabeling buffering for the Open/create file function and only storing files in multiples of the sector size but it does not seem to help. Are there any preferrable USB flash drives one must use? Or am I unaware of any "high speed file streaming" options in LabVIEW?

Sincerley,

CC

https://www.sparkfun.com/products/11225

I'd like to get a cheap copy of LabVIEW at home that isn't tied to work licenses.  The application would be playing around with my kids.

My thought is that this has something to do with dynamic dispatching, but since the data type isn't changing between iterations (when using the shift register) it should be fine.

Attached is the code (LabVIEW 2012).

Does anyone have any insight why I'm having a problem?

Thanks.

Test FPGA.zip

I'm at my wits end here trying to interface with an FPGA. I've currently got it configured as follows:

7813R FPGA card in a LV-RT machine, running LV2012 on host and Real-Time machines.

Compile: Run when loaded = True

Obtain Reference:

• Linked to bitfile 
• FPGA ref bound to typedef
• Run the FPGA VI = False
  

FIFOs (2 host-to-target DMAs) depth initialized after reference obtained.

Code then utilises reference to read indicators, send values to FIFOs and update controls.

On Shutdown: FIFOs stopped, but reference not closed.

My problem: All subsequent runs after shutting down the program (via the shutdown method) will successfully obtain a reference to the FPGA and init FIFOs (no errors generate), but attempts to read any of the indicators, or update any of the controls do nothing. Indicators show default values, and controls are unresponsive. In the past, I've fixed this by recompiling the FPGA, also sometimes by just redownloading it. Since I made some changes to the way data is loaded into the FIFOs (absolutely no changes to anything that ever touched the FPGA reference, purely to the way the arrays are formatted), nothing I do seems to recover the responsiveness.

I've tried: Restarting the RT machine, re-downloading the FPGA (in different orders). I've added close FPGA reference and "Start on Run" to the obtain reference and then restarting and re-downloading. Absolutely nothing has worked. I'm currently in the process of removing "Run on load" (performing a recompile), after which I will add "Start on Run" back into the Obtain reference vi.

I'm at my wits end. Has anyone encountered this sort of problem before, does anyone know what causes it?

I currently have an issue where I'm feeding a relativeley large data set into the FPGA FFT (524288 points) which are computed as 512 1024 sample length transforms (rows of image data).

Despite receiving the correct number of valid inputs (I've checked), the FPGA only returns 522240 points (it's two rows short), can anyone illuminate why this is happening?

The code snippet is shown below.

Under my development environment it runs great, but when installed on the XP Embedded system it will run for a few minutes, and then pop with a very ungraceful "DAbort in ThEvent.cpp" message.

I've tried to track this down to some action or event, but it appears to be relatively random. I had noticed, in older versions of the code, a memory leak, but that's been resolved since and yet the crash persists.

I know XP Embedded is not officially supported, but this embedded installation is virtually a full XP installation, so there shouldn't be any concerns there (I hope). Anyone know where I can start with diagnosis of a crash like this? Google isn't helping, so I need to perform investigative effort but I really can't think where to start!

I have a design on a 7851 that is working in the lab and now there is one big issue.

The system consists of this FPGA card in a PXIe crate with an 8133 controller which on startup configures the FPGA using the "Open FPGA VI reference" VI, parameterizes the FPGA and receives data from it. The "Open FPGA VI Reference" points to the bitstream and was configured to generate a typedef from the interface. The application on the controller uses LVOOP, the class has in its private data control an instance of this generated typedef (actually it's a bit more complex due to other reasons, the private data only holds a reference to the cluster that holds all the data including the FPGA VI reference, but I don't think this makes a difference). Using this instance and the FPGA Read/Write nodes as well as a DMA FIFO the host application interfaces the FPGA. Within the FP interface to the FPGA there is also a cluster holding some numeric and boolean values, lets call it "param_cluster".

The problem is now: I developed it in the lab where it was tested to work. I committed it to SVN (which is used to manage the whole project, essential building block of everything). When I check it out at the teststand to deploy it FPGA Read/Write nodes to "param_cluster" are broken, the error message is "Error: Master Copy for Type Definition could not be found". It's exactly the same error as in this thread http://forums.ni.com...nd/td-p/1496866 . Pitifully there were never clear answers to this. A temporary solution to this problem is to rebuild the bitstream at the teststand and reopen it in the "Open FPGA VI Reference" VI but this cannot be done in the final system. The bitstream used then must be the one tested and verified in the lab.

So anyone has in idea what is happening there?

Cheers,

flintstone

  I have lately run into a problem of insufficient memory. Basicallly the controller is ever running and i generate data and store it in .tdms file every x sec. and every shift (3 shifts in a day) i ftp the file to the host and delete the file. During accumalation of the data the ram continuosly decreases(contiguous memory also decreases as i have a lot of array manupilations and such).

I want to recover this contiguous memory at the end of the shift so that the next shift runs smoothly. this is observed because i saw lot of inconsistency in the data file. Is there a vi which will free up ram and defragment it?.

I cannot use preallocated array because i dont know before hand how many data points i need to store. the data that will be put is in variable time.

Thanks in advance.

Tinkering with my FPGA code today, I ran into a question which I'd never really contemplated before. Say I have an unsigned FXP number with word length = 1 and integer word length = 2. Labview tells me that this gives a maximum of 2 with a delta of 2, so the number can either be 0 or 2.

This makes no intuitive sense to me, the way I understood it, the word length is the total number of bits used to capture the number, the integer word length is the number of bits dedicated to capturing the integer portion, in other words, it kind of defines the "magnitude" of the number that can be captured, the remaining bits are used to give the "precision" to which the number is captured. So how is it even possible for the "integer word length" to be greater than the "word length"?

Insight much appreciated.

Cheers,

Alex

From the NI site it is not listed under LabVIEW for Embedded Applications and doesn't appear to be for sale anymore.

Thanks.

Do not hesitate to post comments on the NI thread or through this forum.

So, a quick question. Suppose I have the High-Throughput FFT in a single-cycle timed loop performing transforms on data-sets 1024 points long. For each set of 1024 points, which should be considered completely independent of each-other, do I need to trigger the reset line on the FFT?

I ask because I'm seeing a weird periodicity in the results of a "find max" type algorithm which is hunting through the magnitude of the frequency spectrum. At worst, the result of this "find max" should be random, not periodic in nature. My guess is that there is some sort of index shifting going on which could be a result of a bad indexing operation (something I can check and fix myself) or as a result of some sort of accumulation in the FFT.

Edit: A quick note, there is definitely no periodic shift in the data itself, it should be more or less constant.

Can anyone shed light on the matter?

Cheers,

Alex

Although it sounds like NI has some promising products on the way I'm guessing it will be too expensive for the hobby market. I've researched a few options and they are all lacking in some way...

Raspberry Pi - Hard to beat $25 for all the features this comes with. Unfortunately it's not available yet and I suspect it will take some time for self-learning material to develop... and to be honest my ventures into linux environments haven't been particularly fruitful.

Arduino Due - Arduino is a fairly mature platform with lots of available content to draw from. The Due is the first 32-bit ARM processor released for Arduino. Unfortunately, following a surge of post-maker faire publicity last fall the Due seems to have fallen off the planet. I couldn't even find references to it on Arduino's web site.

mbed - Another interesting dev platform. Though it is a little more expensive at $60 it has the advantage of actually being able to purchase it. The downside? It uses a web-based dev environment. Thanks, I'll pass.

Other tools I've found are positioned (and priced) as business tools, not hobbyist tools. Has anyone had particularly good experiences with an inexpensive ARM devkit and toolchain?

I've had my FPGA code running for a while now, but I'm hesitant to trust it, because I don't really understand the concept of handshaking and throughput. Say I have the following block of code:

My question is, if the multiply takes 1 cycle/sample to compute (and this goes for all blocks that say they take 1 cycle/sample), does it return its result on the exact same cycle that it receives a valid point (I.e. when divides "ready for input" goes true and a deviated bin element is dequeued from the FIFO).

OR

Does it take another cycle and thus, I should always load the result of multiply (and any other high throughput maths) into a shift register to be absorbed by divide on the following loop iteration?

Thanks for your help.

Alex

Am doing Ph.D in National Institute of Ocean Technology. I have to write a code in labview.

I have to generate a spectrogram and store spectrogram in the jpg file format in crio. The code works on my local PC. When I deploying the same in crio, it didn't work. It returns zero. Also I tried the paths like c:test.jpg or /c/test.jpg; both didn't work. We are using Labview 2011 full professional development system.

cRIO 9025

Chasis 9113

NI 9229

Thanks for the help.

ASAP.

Regards,

Ashokan

When I attempt to build the project, I get the following error.

'LabVIEW: Generic file I/O error.'

=========================

NI-488: I/O operation aborted.

Error 6 occurred at Write to Text File in

niFpgaCompileWorker_SaveStatus.vi->

niFpgaCompileWorker_Status_Publish.vi->

niFpgaCompileWorker_GetStatus.vi->niFpgaCompile_Worker.vi:1

Possible reason(s):

LabVIEW: Generic file I/O error.

=========================

NI-488: I/O operation aborted.

C:\NIFPGA\compilation\TheFPGA_FPGATarget_TheFPGA_0E9FD350\BuildResults.lvtxt

My first thought was that the file size was too long. (I had the project buried in a deep heirarchy with a long job number in the name.) I reduced the size of the FPGA project, target, and folder name then moved the project to C:\ . The name shouldn't be an issue now.

Any ideas?

The error is so generic that it doesn't feel very helpful.

I reckon my question is more windows XPe related than LabVIEW related, but it wouldn't surprise me if someone here has dealt with, or considered this idea before in this arena.

My googling has turned up very little... but I want to know how feasible it may be to turn a box running XPe into a USB device (test and measurement class) that can be recognized by a remote hosting computer - all the while still being able to host USB devices on other USB ports itself for USB DAQ.

Even if someone was willing to point me in the right direction, to documentation or another forum it would be very much appreciated!

Thanks

-pat

http://www.wallstree...a.com/fixcancel

Feedback and comments are appreciated.

i am doing a project in labview ...( HMI) which controls the machine.. user interface..

now what i need is i want to communicate the pc labview with FPGA  some standard communication  protocol...  

it should be faster.... (because i want to do frame grabbing the raw data)

reliable, less hardware , multi slave interface... less communication error... etc so kindly guys give some good suggestions...

The test machine I'm using is a 2.79 GHz Pentium 4, WinXP, 1 GB RAM system with a PCI-7831R card in it. I'm running LabVIEW 8.6.1.

I'm trying to stream data from the FPGA to the PC over a DMA FIFO. I've picked 250 kHz as my current benchmark as that is significantly above where the actual system is going to need to run. The FPGA side uses a fixed time interval (4 usec) FIFO write. The PC side uses two loops, one to read a latched timeout flag in the FPGA and one to read out the FIFO in a 20 msec loop.

This works most of the time until I do something like minimize Windows Task Manager. The CPU usage doesn't blip and stays at ~25%; the number of elements remaining in the FIFO jumps to 30,000+ and I start to lose data points as the FIFO write in the FPGA times out.

I've attached my test code.

I appreciate any light people can shed on this.

Tim

FPGA DMA Test.zip

I just played a little with LV2009 and the FPGA module. I even could compile a small VI with LVOOP in it. Does anyone know some examples for LVOOP on FPGA? Or even benchmarks of the possible hit on size and speed of such code? Currently I don't have access to our cRIO so I can't test myself.

Greetings from Munich

Götz

And can comment on the pros/cons including differences wrt Windows CE & using NI Touch Panel Module - especially graphics?

KB, KB, Dark Side Forum

I am interested to know the differences as the TP Module and Windows CE can be a pig to program compared to standard LabVIEW and Windows XP - don't take my word - go ahead try it

[Cross Post]

thanks,

Bernard

I am new to LabView. I have a very urgent project (which seems to be very simple) but it's not working.

I'm using the PXI-7831R board (will use the 7851R) and LabView 2010.

The goal of my project is to continuously read TDMS files from the computer hard-drive and transmit them using 5 analog output channels. All the channels should be perfectly synchronized. First of all, since I'm working with very large data files, I'm parsing them into smaller files (offline, before the actual transmission). BTW I'm currently working on a version that will perform the parsing on-line - it's not ready yet but from what I see it won't solve the issues that I'm talking about.

In order to transmit all the files simultaneously, I'm using a single DMA FIFO. I'm concatenating every value from the 5 files into an array, transmitting it to the FIFO and then on the FPGA side I'm sending each sample to a different analog output.

I've encountered the following issues:

1. Transmission rate: Though the board spec (7831R) says that the transmission rate is up to 1M, I'm unable to transmit with a rate higher then ~550K without distorting the signal. For example, I use a 75KHz sine sampled at 500KS/sec rate. In that case, if I transmit the sine @1M I should see a 150KHz signal but what I actually see is a ~80KHz signal.

2. When I analyze the transmission spectrum (with MATLAB), I can clearly see 2 spikes at +/-7Hz around the signal. These spikes are extremely bad for my project. I analyzed the files that I recorded (before the transmission) and the spikes aren't there which means that they're caused by the DAC. I managed to get rid of the spikes by not limiting the FPGA clock, but in that case, as I mentioned earlier the signal frequency is wrong.

I think that the 7Hz noise occurs due to the fact that the FPGA buffer is emptied and re-filled. When analyzing the transmission with MATLAB I can clearly see that every ~150ms some samples are missing from the transmission. I tried it change the FIFO size but it didn't help.

My project is attached - please tell me what am I doing wrong.

I will also appreciate a working example of transmitting at 1M (or any other rate) that was verified and prooved to be working fine.

Thanks in advance

DMA output - 5 channels working.zip

1. A large number of hardware I/O and parameters sent to an R-Series card (specifically a PCI-7813R)
2. Internal calculations made in the that are used in multiple other internal subroutines

I pondered and wound up using global variables to store this glob of internal and external values. I've kept pondering as I'm accustomed to considering globals to be akin to "demon spawn and should be avoided as the plague they are." I've poked about example and tutorial code, but everything I've found is too simplistic in that the entire code is a couple of VIs with no connections between them.

How have you structured code to deal with large number of values that have to go various places? Are globals so evil in a FPGA? How have you dealt with sending subsets of a large number of values from subVI A to subVIs B, C and F without creating obstufication or unmanagable code?

Tim

I didn't fail the test, I just found 100 ways to do it wrong. - Banjamin Franklin

I'm using:

1x cRIO-9073 with 1x NI-9203 and 1x NI-9205

1x WSN-9791 Gateway with 3x WSN-3202

1x MBus Modbus converter connected to RS232 of the cRIO

Labview 8.6.1 + FPGA + Real Time

NI-RIO-3.4.0 without Scan Engine

My system runs as a datalogger. Ac mains are measured with 10KHz and the mean of 2 seconds of current and voltage are stored. All other devices are sampled with 2 seconds. A further loop stores that data in an array and after 1 minute it makes the mean for each 10 seconds (5 samples) and stores the result in a TDMS file.

The problem is, that the application starts with memory occupation of about 78,6% (View in System Manager) and with each second it increseas slightly by 0,001% or even less. BUT that's enough that after one or two hours the cRIO runs out of memory and gets stuck. The problem is, that this device is in a remote location and should run for 2 years and I can not go their every 2 hours to reset it manually because it does not respond in remote.

In the screenshot you see the main VI of the cRIO. First of all I have some init stuff, a 1 element cluster Queue which is use like a notifier (single writer=>lossy enqueue and multiple readers=>preview) and a 10 element string Queue which drives the overall init and control finite state machine. This state machine, after init toggles between Idle and Remote with a periode of 2 seconds to read the values of functional global variables which I'm using to control the system in remote. (not really needed much, because it's a "stupid" datalogger application which does not need any user interaction appart from freeing disk space by downloading periodically the tdms data).

The second big loop in the upper part includes 2 timed loops and one while loop to make acquisition and data storage.

1) Timed loop with 200ms periode reads FPGA DMA and elaborates data. If a package of data (2048) values are in memory, a 50Hz single tone frequency will be search to measure AC mains frequency, RMS voltage/ current. This elaborated data is passed into a functional global variable (FGV).

2) Timed loop with variable periode (in this case 2 seconds) reads WSN data, AC data from FGV, Modbus, analog inputs of the cRIO and inserts the data array into a RT-FIFO

3) Reads RT-FIFO, waits 500ms to free CPU if no further element is available. After a variable time (60s) all collected data will be processed and is then stored in a TDMS file. The TDMS reference is opened once and so long the system doesn't loose supply it is stored as FGV. Only after restart the reference will be reopened again.

**************

And somewhere in this code the cRIO is eating piece by piece my free memory :-(. Each SubVI contains allready "Deallocate Memory" but it didn't improve the system. I'm really desperate. Can someone see from the screenshot if I'm using a programming structure or method where some issues with memory are known? I have no idea.... It happens also with an other project, where I just read 5 analog inputs with a sampling periode of 2s. There after 20 days the cRIO is stuck again, means memory is also full. Could the problem also come from VxWorks RTOS behind Labview?

**************

Don't know where the problem comes from and tested allready so many things.... the problem is that is takes hours or day to reproduce the error and that really a problem, because I can never be sure that the system is not running out of RAM memory after some weeks?

Thanks for all suggestions you can give me, I'm really looking forward to any single reply, because otherwise my whole pipeline full of projects won't be successful.

Ciao

Kobe

Compilation Report.txt

PS. if the test does not take time ( small amount of data) the FPGA works fine but if i increase the amount of data the FPGA will start working but after a while the message and the VI mentioned above appears.

I have the question about the best practices how to write the array of 32 bit values into RAM on FlexRIO card.

The arrays can be quite large up to 2 400 000 of elements. there are simple 1D array that are read from HDD. This files are prepared before.

We need to write this array to the specific address in RAM. Because there can be this array read several times we can't use FIFO's.

The problem is if I use the for loop and write into ram Address after address the time for large arrays is big, several seconds.

Do you have better solution or some proposal?

Thank you for your help.

I need to read and log 13 PWM inputs. I've thought about multiplexing the PWM inputs like http://zone.ni.com/devzone/cda/tut/p/id/3254.

But the problem with multiplexing the PWM is that I won't have all the data from the 13 inputs at the same instant which I need.

So I've decided to have 13 loops on the FPGA each of which wait for a rising edge and then a falling edge and write the Ton time into an indicator. There is another 14th loop which reads from these 13 indicators using a local variable and writes into a DMA FIFO. RT reads from the FIFO and writes into a TDMS file.

Is this the best way to do this? Am I unnecessarily taxing the FPGA?

The PWM inputs are all from an infrared temperature sensor which I'm using to measure tyre temperature, which is why they need to be logged at the same instant.

Thanks

Ananth

I'm currently trying to simulate a block of FPGA code which performs an FFT. I am having a lot of trouble getting the simulation to store the output of the FFT

Here's the FPGA code:

And here is where I seem to be having problems with the test bench:

I've verified that the input case works, i.e. the FPGA code produces a graph corresponding to the input code I'm providing to the test bench, but the output case doesn't seem to populate the FFT results global, and I can't figure out another way to look at the results of the FPGA code.

Any help would be much appreciated.

Regards

Alex

Our NI Wireless Sensor Network (WSN) Starter Kit just arrived today.

Within an hour, I had it setup, the LabVIEW WSN Pioneer Module installed, devices communicating and was writing and deploying target VIs for the embedded modules.

On first impressions this seems like a really neat product and is easy and kinda cool to use.

The Kit contains two programmable nodes, the gateway, software and a few inputs (pot + thermocouples)

I have just played with it on a PC but I am looking forward to connecting it up to a cRIO

You can get a IP64 enclosure for them as well.

Is anyone else using these?

What are your thoughts?

I am trying to simulate a FPGA VI with a "normal" VI. Up to now that is working quite well, but now I have weird effects reading a port. One Port (8Bits) is read out from two(!) different parts of the FPGA VI. The one part is using the higher 4 bits and the other is using the lower bits. With the Simulation I try to count these Nibbles up or down separately. The nibbles should wrap around. (E.g. 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1...). The problem in my simulation is that sometimes, especially in the beginning, one step is left out (e.g. 0 1 3 4 5). This error is not happening if I am disabling one of the parts of the FPGA VI where the port is read out. So if the port is only read out from one(!) part in the FPGA VI, it works without these "errors". The most important parts of the simulation VI ist attached. I hope someone can help.

Greetings

Tim

Hi

Does anyone knows if LabVIEW DSC works on XP embedded?

These two posts are interesting: WinCE post, cRIO post.

Links DSC Help, shared variable,

Regards

JG

Regards

souske

has anyone run any labview applications in single board computers? i wish to develop few applications for industrial use, using labview. i can build the application using application builder and load application as well as runtime enginer in SBC. Please help me if some one has run any model SBC a labview applicaitons. I wish to know which company and which model SBC can handle labview application.

regards,

Nabhi

I am working with FieldPoint. Everything work fine, until I built the .exe file. When I click on the FieldPoint IO Point I see the browse ... But when I select it there is a pop up window appear for 1 sec then it disappear. I can not select the channel. Can anyone tell me how to fix this?

THank you,

Thang Nguyen

what do you think about the possibility to run labview on this device?

thanks,

Alessandro

Does anyone have any experience with LabVIEW's Embedded Development Module? My company is considering it for use in programming a Colibri XScale PXA270. I am trying to get impressions from persons who don't work for NI as to whether or not this module is a reasonable way to go or if we should just stick to C when programming these devices.

Thanks for the help!