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Try interleave array?

Yet another program: list I/O names and methods/properties available for each of them. Inputs for the VI: LabVIEW project path, FPGA target name, log path (for writing the info). A sample of I/O name lines from the log: These '+'-es at the beginning of each line tell that looking for methods/properties of the I/O item found the item and no error resulted from the operation (each '+' has a different meaning, but I was getting +++ only). First 10 names have no leading '/' - they were found as non-alias names, all remaining - as alias names. Here crio_Module5 is NI9476, it has a "Check Output Status" method and 3 properties (these properties common to all C-Modules, and they are read-only, it is shown by '(R)'); crio_Mod6 is NI9205, it has 4 methods and 15 properties; crio_Mod1 is NI9871, it has 3 properties and no methods; its Port1 has 3 methods and several properties, some are read-only (R), some write-only (W), some bidirectional default-write (Bw), a (Br) would mean bidirectional default-read. Here crio_Mod7 is NI9208, it has 4 properties (an additional is "Conversion Time"). Then alias I/O items follow: "Chassis Temperature" can be read, "Sleep" can be read and written, as well as "System Reset" and "USER FPGA LED", "USER Push Button" can be read, and "Scan Clock" has 2 methods and 2 properties. Here crio_M3 is NI9477, its DO0 signal can be read and written, as well as DO0 signal of crio_Module5 (NI9476); crio_M4 is NI9425, its DI signal can be read, as well as crio_Mod6 (NI9205) AI0 and AI31 signals. The NI9205 has also Trig signal (read-only), DI0 signal (read-only), DO0 signal (write-only). And finally few CLIP signals: "/v1/SignalList/a.b0" is "a.b0" of CLIP "v1" (write-only), "/v1/SignalList/aw" is "aw" signal of the CLIP (read-only). Attached: a VI used to produce the list and its BD picture. io_names_list2l.vi

The only thing I have found to work is to maintain separate projects for 32-bit and 64-bit and have them each build into a seperate location on disk. Anything else is going to mess up your projects almost beyond repair possibilities. That applies to both the projects to build your PPLs, possibly one project per PPL in the case I worked on, as well as for the applications using those PPLs. Using Symlinks to map the build locations of the PPLs to a common path that is referenced by all the projects making use of PPL dependencies (including PPL build projects), helps with maintenance of the projects as they all only need to reference a general location for dependencies rather than an architecture specific location.

Hi all, I'm looking for help to increase as much as possibile the speed of a function that reshape a 1D array from a 4 channels acquisition board to 4 2D array. The input array is: Ch0_0_0 - Ch1_0_0 - Ch2_0_0 - Ch3_0_0 - Ch0_1_0 - Ch1_1_0 - Ch2_1_0 - Ch3_1_0 - ... - Ch0_N_0 - Ch1_N_0 - Ch2_N_0 - Ch3_N_0 - Ch0_0_1 - Ch1_0_1 - Ch2_0_1 - Ch3_0_1 - Ch0_1_1 - Ch1_1_1 - Ch2_1_1 - Ch3_1_1 - ... - Ch0_N_M - Ch1_N_M - Ch2_N_M - Ch3_N_M where, basically, the array is the stream of samples from 4 channel, of M measures, each measure of N samples per channel per measure. First the first sample of each channel of the first measure, than the second sample of each channel.... Addtionally, I need to remove the first X samples and last Z samples from each measure for each channel (basically, i'm getting N samples from the board but I only care about the samples from X to N-Z, for each cahnnel and measure). The board can be configured only with power of 2 samples per measure, hence no way to receive from the board only the desired length. The end goal is to have 4 2D array (one for each channel), with M rows and N-(X+Z) columns. The typical length of the input 1D array is 4 channel * M=512 measure * N=65536 samples/ch*measure; typical X = 200, Z = 30000. Originally I tried the following code: and then this, which is faster : Still, every millisecond gained will help and I'm sure that an expert here can achieve the same result with a single super efficient function. The function will run on a 32-cores intel i9 cpu. Thanks! Marco.

This is why it takes me hours to make an ECL build that works and is one of the many reasons only Windows is now supported (can load from same dir). Even then. I have to fight VIPM to get things in the right places. I refuse to do #2.

5.0.1 and in the meantime 5.0.2 has been since released. One issue, but that is not really new and existed before: Don't disable mass compile after install, it may take some time but it sure fixes stale shared library paths in the VI and I have so far not found a way that makes those paths automatically fixup at package creation, since the path seems to need to be absolute. The two possible approaches I'm currently considering: 1) use a so called Symbolic Path (/<user.lib>/_OpenG.lib/lvzip/lvzip.*). Disadvantage: - only works if installed into default location 2) use Specify Library Name on diagram for the Call Library Node and calculate its path at runtime. Disadvantage: - makes the shared library be not a visible component to the VIs, so that the shared library needs to be added explicitly in every application/shared library/assembly/source distribution build in order to be available in such - extra execution time for the dynamic calculation of the path

Hi, seems I found a solution. The program should do the following: use Invoke Node for This Application constant to open a project with an FPGA target; use Property Node on the project ref to get targets; look for a matching FPGA target (in my example I also compare target name, so it can handle a project with many FPGA targets if it happens), closing the other target refs; use Property Node on the selected target ref to get its Application ref; create (or open) a VI for the Application, open its BD window, gets its BD ref; (the above action is in the upper line of my VI) use eio_Utilities_GetNonAliasNames.vi on the Application to get names to be used: - "persistent names" output gives names (array of strings) that can be used, - "resource names" and "display names" (arrays of strings) can be used to find an element in the "persistent names" - choose e.g. Mod1\Port3 in display names, and use its index on the "persistent names" to get required persistent name; the persistent name is to be used as "item" for EIOPlaceDownEIOMethodNode.vi and for EIOPlaceDownEIOPropertyNode.vi - the "item" is in "State" cluster; few other elements of the "State" cluster, common for these both "Place"-s, are: "alias selected", "DoSpecify", "ref in wired", "ignore ref inputs"; the "alias selected" must be False, the "ref in wired" must be True; do the other matter? I don't know; making a Method needs also a "method name" to be set, valid methods for an NI9871 serial port are "Clear Rx FIFO", "Read Byte", "Write Byte"; for making a property I specified "id counter" = 1 (is it needed? I don't know), and of course the "properties" - an array of clusters, in each of them I set: "name" (string), "direction" (enum, I used read or write), "terminal id" (int); each "Place" needs also Diagram (I used the BD ref), context (= Application ref), and "Position" (a cluster containing left-top corner coordinates); each "Place" returns a "Terms[]" - an array of terminals - I show some info on them. Attached files: a picture w/ BD and FP, a PDF containing the BD, the VI (LabVIEW 2018). ni9871cmp.pdf ni9871cmp.vi

Hello, I have a problem with my two VIs. The first VI is for data acquisition, and the other VI is for data recording. I am working with CompactRIO, and communication between the CompactRIO and my PC is done via an Ethernet cable. For the acquisition chain, there is an acoustic sensor attached to a rod and a hammer. On the second VI, I want to record the data right after I strike with the hammer to capture the vibrations. How can I achieve this? Additionally, I want to define a specific number of samples, but whenever I set it, the receiving VI freezes.

you could try this property saver. its pretty old. See the examples in the palette that gets installed konstantin_shifershteyn_lib_property_saver-1.5.0.4.vip

Thanks, I've solved that problem.

Hello, I would like to save parameters for UI elements and load them when the program exits. What's the easiest way to do this? I think UI element parameters might include things like the color and thickness of graph lines, tab positions, and the maximum and minimum Y values for the graph.

Use the File Dialog express VI on the File IO >> Advanced palette. You can configure this to prompt the user for a file path then wire that into the open.

When I use "Open VI Reference" to run a VI file, LabVIEW looks for subVIs when there is a subroutine in the called VI file. When I run this program in RunTime, it says that the subVIs are not found, but I can find the missing subVIs in the development environment, I want to know how to set the path of RunTime to find the subVIs.

I need a program in FPGA to control a hardware, without mediation of RT part - and I plan to use LabVIEW for the FPGA only. Because of this, there is no place for using VISA. I want to have the same code for each serial port - they are to be configured differently, but the configuration should be passed as data to the code that is to set it to these ports. FPGA has access to these ports (the VISA would access them via FPGA), but I don't know how to place a port name in LabVIEW - the only way I know is to select manually the port resource for each Property and Method used to access the port. And I don't know how can I programmatically verify that the correct port resource is selected in each place, as I have no way to read it.

Thank you Shaun for the reply 🙂 Today the best of the day is gone, I hope I will have time soon to give it a try.

Hello Rolf, thanks again for the great help! It's kind off busy here so I was not able to reply earlier.. Well I am in a bit of luck this time I did find some documentation and the compiler used is "MSVC2019". It is written in C++ and it: "exports a pure C interface", I like the word pure as it reminds me of clean air, oceans without plastic and being young, in this context however I can not really understand what is meant. maybe you can give a global idea? If I read this text I think it might be wise to turn error handling off? At this time I did set it at maximum, hoping to get some information about things that might went wrong. Thank you for the remark, In the real code I do check if the handle is not 0 if it is zero I return a error code to Labview. If the pointer is 0 I also return a error code to Labview Thank you for the remark. I need to read this remark again when it is not too late, my energy level is kind of low now at the end of the day. I will try to find the example I started with to go with your remark. I think I understand what you write. The dll I wrap in my own dll uses a callback to send error and status massages. I can see them in Labview now 🙂 . I think however it is better to use this info in the C code eventually e.g automatic stop logging when there is an error related to the logging. I need to find out the best way to do this though. And even if I can use the error and status messages it would be really helpful if there is something going horrible wrong with the dll, something I did not think about, the dll will not be able to make Labview crash, I rather would have a message telling something like: "Unknown error at dll, program halted.." , better to have a ugly way of telling something went wrong than a crash-ing way which closes down Labview. If this would be possible please let me know. Maybe I can at least use some kind of exception handling when loading / running the functions of the dll I try to wrap? Thanx for the help!

Update To get it to work I had to downgrade to version 6.0.0.25 - OpenG File Library (from 6.0.2.28) 6.0.0.18 - OpenG Array Library (from 6.0.1.20) May be this helps someone else 🤷‍♂️ Thanks

Hi I upgraded OpenG File, Error and Array Libraries to the latest version using VIPM and my project didn't automatically link as suggested "Important: Callers of this package will relink automatically to the new Library (openg_file.lvlib) that contains this package. However, if you subsequently downgrade this package to version 5.x or older, your callers will need to be manually relinked to the older version (without the Library namespace)." The problem is the toolkit is used in so many places it may take days to relink by hand, as well as other VIPM libraries that reference the library. I am using LV2022Q3 64bit Tried clearing cache and on my dev laptop but same result, I cant remember what version I had before upgrade so I will try that first just to get it working again. Any assistance will be greatly appreciated Thanks in advance!

Can I use this module directly? Is it possible to implement a control algorithm by discretising all the transfer functions in the graph and representing them with this module?

Well. There's a few problems but the reason it's not showing the next image is because you increment the counter during acquisition until it's 300 and when you start the next acquisition it indexes into the path array at 300 (which yields Not A Path). You've confused your 30 second timer with the file index. Make a proper timer with a time function and increment the index on stop.

have been trying to get this code to work for days if any of yall can help it'd be appreciated :). But in summary the program is supposed to simulate record ekg data points(this is basically just the simulated code). and cycle through 10 pictures 30 seconds each. I have almost everything done it just doesn't properly write the data points or display the next image. I feel like this is a relatively simple fix but i cant figure it out. Heres a link to my vi "https://drive.google.com/drive/folders/140W4QPNG7cZY1MwxS-ReREIstQ_OgN2J?usp=sharing"

Thank you very much for your reply! I'm using a compact RIO.I have to implement this control algorithm on the FPGA side. May I ask how this is realized as you said（ break it down into developing your own nth order derivative and integral functions） Can you give me a simple example? thanks.😃

If you use the chroot trick that NI/Digilent did for the Linx/Hobbyist Toolkit it is theoretically doable but far from easy peasy. And you still have to sit down with the NI/Emerson lawyers as I told you before. However I doubt you want to run your Haibal library in a specially compiled Debian kernel running in a chroot inside your Jetson Linux distro. That is necessary since the entire NI library tree and LabVIEW Runtime is compiled for the arm softeabi that NI uses for their Xilinx XC7000 based realtime targets. And yes you can NOT run a LabVIEW VI without LabVIEW runtime on the target! Period! And that NI did put the NI Linux RT source online has nothing to do with that they want to be nice to you or let you build your own LabVIEW realtime hardware but simply because it is the most easy way to comply with the GPL license requirements for the Linux kernel. But those license requirements do not extend to any software they create to run on that Linux kernel, since the kernel license has an explicit exemption for that. Without that exemption there would simply not be any commercial software to run on Linux. And I understand what you want but that does not make it feasible. I WANT to win the jackpot in the lottery too but so far it never happened and quite certainly never will. 😀

Good morning Ha I hadn't seen this answer! I don't understand the point of putting NI Linux RT online? What's the point ? I just want to simply deploy my code to this target that has a GPU. IN fact what I want is to deploy LabVIEW code on my Jetson target. I don't want to install LabVIEW RT on my target, I just want to deploy my code as if I were on a machine. Is this possible on an Ubuntu Arm target as was done on Rasberry PI. The idea is to use the Jetson GPU for HAIBAL deployments. I asked NI but they didn't answer me. who could be our contact at NI ?

Yes but you'd need to define "reliably". I think there would be few milliseconds of jitter and probably a minimum of about 4ms.