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How to improve performance with FPGA generate frequency.


Thang Nguyen

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Hi,

I am working on a project with cRIO. My VI runs in FPGA.

What I do in PC is calculate the frequency then convert it to period and convert to uSec (multiply by 1,000,000). This value is sent to FPGA by the FPGA interface.

In FPGA, I just do as in the screenshot.

I still have some different in the value. The value I calculate is 60.4 Hz and the signal I received from the scop is 60.2 Hz. I just wonder if I can make it better. This lead to a different of 0.1 mph or 5 r/min depend on signal.

I highly appreciate any help.

Best regards,

Thang Nguyen

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The first this I would do is replace the divide by 2 with a Right Shift, as a divide is a very expensive operation on an FPGA. The next thing I would do is calculate Cycle Period in Tick before sending to the FPGA, as this would increase your resolution. Though the frequency to are dealing with that doesn't seem like it would have much of an effect.

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