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cRIO Wfm FPGA error 65100


kull3rk3ks

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Hello there!

 

I'm currently working on the control of a machine that does a specific measurement while the sensor (composed of several strain gauges) slides along a sled.

 

I would like to acquire the sensor Data and to relate it to the position of the sled. The machine also has simple User inputs as Buttons and simple outputs as LEDs. The motors are controlled by relais which are connected to DOs.

 

I wanted to use the cRIO Wfm reference library for my project because it seems to be great at this task.

 

My current problem is that whenever I try to start a measurement, I get the error message

 

CompactRIO:  (Hex 0xFE4C) You have entered a data rate that is not supported by the selected module and oversample clock frequency.

 

As a matter of fact though, I know that the Delta sigma strain gauge modules support a sampling rate of 10.000S/s but I seem to get the error from the FPGA.

 

I'll attach my FPGA VI and the Measure VI (which is normally located inside a statemachine) for your reference. - all of them written in LV2012.

 

I also get the same error when Using the example VI provided in the RIO Wfm Library.

 

Thank you for reading and eventually helping ;)

Untitled 1.vi

Measurement.vi

FPGA-Main.vi

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What hardware modules are you using?  Do they support the high data rate you desire?

 

Try slowing down the sample rate to a very low value to see if the error goes away.

 

Neville.

 

I'm using the NI 9236 quarter bridge modules, which should support 10kS/s

I'm also using an NI 9207 to get the position information from a sensor.

 

Setting the sampling rate to 1024 solved the data rate error. I do get another error now: 

Error 537952 occurred at rwfm_AcqRead.vi

 

Possible reason(s):

cRIO Module Underflow:  This error occurs if post-processing code on the FPGA VI cannot execute in one acquisition period.  You must lower your sample rate or reduce the amount of post-processing performed on the FPGA.

 

There is no post-processing that I know of performed on the FPGA. Anybody got a hint?

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  • 2 months later...

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