NI FPGA Timekeeper and IRIG protocol

[Falevoz Y.]

Hi,

 

I have to deal with IRIG B protocol on a compat RIO. It's a 9074 and the IRIG signal is wired on a 9402. I searched on the NI website and found 2 libraries that seems to decode IRIG :

• IRIG-B Implementation in LabVIEW FPGA
• FPGA Timekeeper

I played with the first one and succeed to get day of the year and hour, but not the year. 

 

As the second is recommended by NI to be used with 9467 and it is said to be compatible with IRIG protol ("The NI FPGA Timekeeper is LabVIEW FPGA IP designed to integrate the CompactRIO onboard field-programmable gate array (FPGA) clock with external timing sources such as SNTP, IRIG-B, and GPS."), I thought it would be a better solution.

 

My problem is that there is no example of the use of timekeeper with IRIG protocol and I don't know how to use it in this way. Does anyone has already use timekeeper with IRIG B protocol and can give me an example?

 

Thanks in advance

 

BR
Yann

[viSci]

I once used the PXI-6683 and the cRIO timesync driver which supports IEEE1588 and IRIG.  I used a small PXI chassis to sync multiple cRIO's using ethernet based 1588.  I initially experimented with IRIG but went with GPS inn the end. 

[smithd]

I don't personally know of anyone in my group using IRIG with the timekeeper but it might help to better explain what it does. The timekeeper gives the FPGA a sense of time through a background sync process and a global variable which defines system time. It doesn't know anything about time itself -- its simply trying to keep up with what you, as the user of the API, say is happening. To give you an example with GPS, the module provides a single pulse per second and then the current timestamp at that time. You're responsible for feeding that time to the timekeeper and the timekeeper is responsible for saying "oh hey I thought 990 ms passed but really a full second passed, so I need to change how quickly I increment my counter". The timestamp is not required to be absolute (it could be tied to another FPGA, or to the RTOS), you simply have to give it a "estimated dt" and "true dt", basically. With that in mind, if you can get some fixed known signal from the IRIG api you mentioned, the timekeeper could allow you to timestamp your data. It can theoretically let you master the RT side as well (https://decibel.ni.com/content/projects/ni-timesync-custom-time-reference) but I'm not sure how up-to-date that is or if that functionality ever got released.

[Falevoz Y.]

Hi,

 

Thanks for your answers. With your explanations, I think that the FPGA IRIG-B decoder match better for what I want to do. 

 

I played a little more with it, and it seems that it can do the job with a few modifications.

 

BR

Yann

[JamesMc86]

Just found this and thought it was worth a post for posterity.

 

The FPGA timekeeper is timing source independent. It's like the backend, you give it a time and it will synchronise to it, the main benefit is it will manage servoing the time, so rather than one big step change, any difference is corrected gradually.

 

You then need a time source to send to this library, this is where the IRIG-B decoder would come in.

[Barani Ram]

I have the same setup as like Falevoz.Y but a CRIO-9036. Once i wire to 9402 there is no change in values? Can you guys tell here did i make...

The labview version i'm using is 2018..

Edited July 30, 2018 by Barani Ram