Using Sub-VI in FPGA possible?

[ExpoEra]

Hello,

I have a few FPGA VI's that contains AI, AO, or DO (the way I wanted to group them). Now, I have put these FPGA VI's as sub VI's in a top-level FPGA VI, and have linked them up like you normally would in other non FPGA Labview programs. Then, I would compile it, and put a Open Reference, Read/Write, Close Reference, in the RT VI. And.... it doesn't work. Obviously, I am doing something wrong.

Can someone teach me how to do it? It would be rather crazy to try to fit all 96 DIO controls into one top-level FPGA VI. Thank you.

[ned]

QUOTE (ExpoEra @ Sep 8 2008, 08:23 PM)

I have a few FPGA VI's that contains AI, AO, or DO (the way I wanted to group them). Now, I have put these FPGA VI's as sub VI's in a top-level FPGA VI, and have linked them up like you normally would in other non FPGA Labview programs. Then, I would compile it, and put a Open Reference, Read/Write, Close Reference, in the RT VI. And.... it doesn't work. Obviously, I am doing something wrong.

Can someone teach me how to do it? It would be rather crazy to try to fit all 96 DIO controls into one top-level FPGA VI. Thank you.

Are you trying to open a reference to a subVI, or to the top-level VI? I don't think you'll be able to open a reference to a subVI if you've only compiled the top-level VI. Are you loading the appropriate VI into the FPGA and running it? Have you probed the error outputs from the Open Reference, Read/Write, etc functions, and if so, what error occurs?

[ExpoEra]

QUOTE (ned @ Sep 9 2008, 06:38 AM)

Are you trying to open a reference to a subVI, or to the top-level VI? I don't think you'll be able to open a reference to a subVI if you've only compiled the top-level VI. Are you loading the appropriate VI into the FPGA and running it? Have you probed the error outputs from the Open Reference, Read/Write, etc functions, and if so, what error occurs?

I only compiles the top-level VI, and I open the reference to the top level VI. I use only call the subVI from the top-level VI.

[ned]

QUOTE (ExpoEra @ Sep 9 2008, 11:32 AM)

I only compiles the top-level VI, and I open the reference to the top level VI. I use only call the subVI from the top-level VI.

Looks like this got http://forums.ni.com/ni/board/message?board.id=170&thread.id=353884' target="_blank">resolved.

In the future, please provide a link to other forums where you've posted the same question.

[LAVA 1.0 Content]

QUOTE (ExpoEra @ Sep 8 2008, 07:23 PM)

Can someone teach me how to do it? It would be rather crazy to try to fit all 96 DIO controls into one top-level FPGA VI. Thank you.

Just as an FYI,

You could wrap 96 DIO values into three U32 integers and keep the interface very simple. On the FPGA you can convert each U32 into an array of Booleans to pass to the I/O node. The same works for inputs as well. Converting a U32 into an array of 32 Booleans on the FPGA takes no additional time or space as the U32 is really an array of 32 bits already. It is simply a different representation in LabVIEW, but not on the FPGA.

[crelf]

QUOTE (LV_FPGA_SE @ Sep 9 2008, 02:01 PM)

You could wrap 96 DIO values into three U32 integers and keep the interface very simple.

That's a really good point. :thumbup:

[ExpoEra]

QUOTE (LV_FPGA_SE @ Sep 9 2008, 11:01 AM)

You could wrap 96 DIO values into three U32 integers and keep the interface very simple. On the FPGA you can convert each U32 into an array of Booleans to pass to the I/O node. The same works for inputs as well. Converting a U32 into an array of 32 Booleans on the FPGA takes no additional time or space as the U32 is really an array of 32 bits already. It is simply a different representation in LabVIEW, but not on the FPGA.

This could be useful. :thumbup: