Ale914 Posted February 25, 2009 Report Share Posted February 25, 2009 Hi i have a 7813R here and i need to use it a se 8 different RS232 (of course at TTL levels) I wrote the code to manage one serial and works so i decide to multiply this code for 8 obviously modifying the physical pin associated to each but at compilation time this "monster" don't compile, take an enormous amount of time only to inizialize all vi needed (1033 VI!!!! ) Have you any suggestions? never try to make somethings similar? Thanks Quote Link to comment
JohnRH Posted February 25, 2009 Report Share Posted February 25, 2009 QUOTE (Ale914 @ Feb 24 2009, 03:42 AM) Hi i have a 7813R here and i need to use it a se 8 different RS232 (of course at TTL levels)I wrote the code to manage one serial and works so i decide to multiply this code for 8 obviously modifying the physical pin associated to each but at compilation time this "monster" don't compile, take an enormous amount of time only to inizialize all vi needed (1033 VI!!!! ) Have you any suggestions? never try to make somethings similar? Thanks Making the leap from 1 to 8 seems ambitious. It may be useful to try just two. Quote Link to comment
crelf Posted February 25, 2009 Report Share Posted February 25, 2009 QUOTE (JohnRH @ Feb 24 2009, 10:21 AM) Making the leap from 1 to 8 seems ambitious. It may be useful to try just two. Yeah - replicating functioning code on FPGA is pretty straight-forward. Are you running out of gates? Can you post your code? Quote Link to comment
Ale914 Posted February 25, 2009 Author Report Share Posted February 25, 2009 QUOTE (crelf @ Feb 24 2009, 11:59 AM) Yeah - replicating functioning code on FPGA is pretty straight-forward. Are you running out of gates? Can you post your code? Yes i know that we have to use carefully the FPGA but 8 serial is my goal so... i don't know if i go out of gate because i stop the compilation after 1 hour because seems that compiler was enter in an infinite loop on a range of actions. This night i'll try again after a minor modification on the code, NI suggest me to make a complete copy of the single 232 code including all the sub-VI called in order to avoid resource sharing between parallel executions, i have a share VI maybe this can resolve the issue. Quote Link to comment
Ale914 Posted February 28, 2009 Author Report Share Posted February 28, 2009 the trick suggestd by NI works. I build an FPGA with 8 serial 4 spi and tens of DIO using 45% of 1Mgate FPGA, compilation time about 45 minutes Quote Link to comment
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