FPGA digital output state

[jcarmody]

I'm developing an ATE that needs to communicate with a UUT that contains a microprocessor with a HOLD line. I can manipulate the UUT as long as I keep that pin high; the microprocessor takes over as soon as I drop it. These UUTs haven't had their programs loaded by this time (that's part of my ATE's job) so a watchdog takes over and the UUT isn't addressable until I cycle its power. (There are a few other lines/states that I need to maintain in order to conduct my tests.)

The problem I have is that I have to do a bunch tests and I use a few different FPGA programs to do them. I believe that the digital outputs are dropping when I push a new program to the target and I loose the control lines that allow me to work. I can regain control by resetting the outputs and cycling power every time I change FPGA programs, but I'd rather not (it just doesn't seem right.) My current solution is to take all of the individual programs and unpack them into one Uber-FPGA program (I'm compiling that now) but the block diagram is large and it hurts me when it doesn't fit on one screen.

Is there a way to keep the digital output lines from dropping when I change programs?

Thanks,

Jim

[LAVA 1.0 Content]

QUOTE (jcarmody @ Feb 28 2009, 08:53 AM)

Is there a way to keep the digital output lines from dropping when I change programs?

Jim,

I'll check on this Monday when I get back to the office. Can you let me know which HW and what LV version you are using?

[jcarmody]

QUOTE (LV_FPGA_SE @ Feb 28 2009, 03:30 PM)

Can you let me know which HW and what LV version you are using?

I've got a PXI-7813R connected to a cRIO-9151 expansion chassis containing two NI-9403 DIO modules, and LabVIEW 8.6.