foxman

Thanks, Rolf for the explanation.

Hi colleagues, I need some help. Description: it's necessary to launch an app startup.rtexe on a CRIO 9075 (OC VxWorks) then launch a second app app.rtexe from the first one and close first app. Seems System Ecex.vi might be a great solution, but this function is not available in a palette for RIO which is based on VxWorks. Maybe anyone could help me or share links with relevant information. Thanks, Vadim.

Hi guys, There is a task to acquire data from analog sensors using cRIO 9076 + NI 9234. The task is solved with FPGA and FIFO buffer (code segment is attached). Sample rate is 200 Hz. I disconnected all sensors. During debug I have an issue of appearing "bursts/needles" in the data. I was not able to find out a reason for it. What is typical, when I start topLevel VI and it receives the first package, the "needle" immediately occurs in the data (see graph in the upper left corner) and this is repeated in 8 out of 10 cases. The needles appear without any specific periodicity and affect all channels at once. Has anyone come across this behavior or maybe know what it might be connected with? P.S. MasterTimebaseSource parameter is set to Mod1 for all modules. I attach an example of real buffers for viewing in VI. data.vi

Thank you for your help! I have gotten a necessary result with max sample rate (500 kHz).

Thank you for link. Yes, sure, I'm using FIFO, but I don't know as I can realize correct synchronization without data skips on fast speed.

Hello colleagues! I have a next task: It is necessary to get analog data from 4 ADC channels of myRIO with max sample rate. As we know myRIO has max rate 500 kS/s for all channels. So we have 125 kS/s per channel (500/4). It's good. A question in the next: how I can send data from FPGA target to RT in this case? I have tried to use large size FIFO buffer (target to host) but got compilation error. As I understood FIFO buffer doesn't use external memory for data storage and uses FPGA resources. The next step I think to use max available size buffer and interrupt on host when buffer is full, but in this case I will probably get skips in data stream, because interrupt requires about 400 us. Can I read data from buffer on RT level with invoke node in parallel data writing on FPGA target? Will there be an overlay in this case? And where I can read any info about fast data logging with RIO platform? choose files... Click to choose files Thank you for your help.