Main-vi.tifHi Rolf,
The IT department check my PC and FPGA network connection and they confirmed that all good from that side. They said the error is becasue of the PC-FPGA connection.
However the code worked well for a couple of months, I think now one of my PC or FPGA are slow, so they cannot shake hands, and consequently the code assumes that as "peer closed connection". I have added all the diagram on my Main.vi. Please tell me what would be the first step of debugging the code?Main-Main.tif
Main-vi.tif Main-Try_to_Connect.tif Main-Idle.tif Main-Initialization.tif Main-StopConnection.tif