lavalolo
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Posts posted by lavalolo
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Hello,
Is there a way to use the "FPGA Reference" in different Host Vi's without using the "Open FPGA Reference" each time ?
I tried this with LabVIEW Globals but got an Visa Poke... error.
I have a state machine running down on the fpga card and control the states with different host Vi's.
I use different host Vi's because i build an dll out of the host vi's and so get several (C-)functions which i call
in a CVI project.
This works great, but the bad thing is the execution time. Each "Open FPGA Reference" needs about 90..110ms
and this is really to much for the project I'm working for .
I'm looking forward to every reply concerning this topic !
Thanks in advance, Andreas
Sorry, i posted to early, my mistake.
After writing the HW reference to a LabVIEW Global i closed the reference at the end of the Vi.
So the reference was no longer available when calling it from another VI .
Now it works great, execution times are about 300 us... :thumbup:
Andreas
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Hello,
Is there a way to use the "FPGA Reference" in different Host Vi's without using the "Open FPGA Reference" each time ?
I tried this with LabVIEW Globals but got an Visa Poke... error.
I have a state machine running down on the fpga card and control the states with different host Vi's.
I use different host Vi's because i build an dll out of the host vi's and so get several (C-)functions which i call
in a CVI project.
This works great, but the bad thing is the execution time. Each "Open FPGA Reference" needs about 90..110ms
and this is really to much for the project I'm working for .
I'm looking forward to every reply concerning this topic !
Thanks in advance, Andreas
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Hi,
this is my first post in this very interesting forum,
so HELLO to all of you.
And here's my first question:
=======================================================================
Recently i had a strange behaviour with one of my LabVIEW VI's concerning execution order
with respect to the "error cluster" flow.
Is it right and always the fact , if an active error (error status = true) arrives at an (error in) input
of a following Vi or property node, then the code in this Vi (or property node) will not be not executed ?
I know that i can control this in Vi's written by myself and that i also can find out this by debugging
the code in most cases.
But i wonder if there is a general rule from National Instruments concerning the flow and behaviour
of the error in and out wires.
=======================================================================
I'm looking forward to every reply concerning this topic !
Thanks in advance, Andreas
FPGA Host Vi Programming Slow....
in Hardware
Posted
[ LabVIEW 7.1.1 , FPGA Module 1.1 ]
Hi,
i have an very annoying effect when programming a host VI to control an existing fpga VI.
On each click, loop, read/write control, that i place on the block diagramm, the windows
sand glass appears for several seconds forcing me to wait ......
Anyone an idea why ???
Andreas