Artefacts with PWM Demodulation

[PitchNancy]

Hi,

I use FPGA's counter input for PWM demodulation. My base PWM frequency is 1kHz. I use the tick count VI for the pulse width and period measurement. Tick count clock is 40 MHz, and 16 bit r

[elyness]

What do you mean by "artefacts"? Could it be that your counter is overflowing? At 1kHz, a 40MHz counter reaches 40,000 if it starts at zero, approaching the 65,535 limit.

[PitchNancy]

What do you mean by "artefacts"?  Could it be that your counter is overflowing?  At 1kHz, a 40MHz counter reaches 40,000 if it starts at zero, approaching the 65,535 limit.

4609[/snapback]

Thanks, I did not think of this problem !!!

After correction I do not have any more insane peaks.

But now my problem is the limitation of the band-width by using IRQ. I don't understand why it's impossible to use DMA transfer.