How to implement fractional decimation with 32SPC?

[ZSL]

Hello there,

I have a problem that I can't solve on my own, and I hope to find the answer here from you.

Now, I need to upgrade a product's functionality, which requires using LabVIEW's built-in fractional decimator or interpolator sub-VIs, but they only support a maximum of 16 parallel channels, whereas I need 32 SPC.

https://preview.redd.it/how-to-implement-fractional-decimation-with-32spc-v0-32cn8uozfsle1.png?width=1533&format=png&auto=webp&s=fa46059a51b97eb14ab914ad698c8a15d2ed74c8

I have a project called "IP Test" that uses 16 SPC fractional decimator, and it runs on the PXIe-7915.

https://preview.redd.it/how-to-implement-fractional-decimation-with-32spc-v0-ucua5z9vgsle1.jpg?width=3024&format=pjpg&auto=webp&s=8460e92df12f5d7588f77d84e41a2e2557360afb

Here is the main interface. After running the program and triggering with the decimat.rate, you can see the IQ waveform.

https://preview.redd.it/how-to-implement-fractional-decimation-with-32spc-v0-0tw4vjifhsle1.jpg?width=4032&format=pjpg&auto=webp&s=b609d0b6dbf0fe61975a4ab9c09f2230375295c2

In the following FPGA Main.vi program, I set the I channel to a DC value of 0.5 and the Q channel to 0. After passing through the frequency shift module, the output is connected to the data in interface of the 16 (or 😎 SPC fractional decimator.

https://preview.redd.it/how-to-implement-fractional-decimation-with-32spc-v0-y1aaxz46jsle1.png?width=1647&format=png&auto=webp&s=b522436e22917b2f89d46869c57708f044119a3d FPGA Main.vi

In my understanding, this program sends 16 IQ data points (16 SPC) in parallel to the fractional decimator during each cycle. It can be seen that the frequency shift module supports 32 SPC, but the fractional decimator does not. This is the problem I need to solve.

https://preview.redd.it/how-to-implement-fractional-decimation-with-32spc-v0-kwncautwmsle1.jpg?width=4032&format=pjpg&auto=webp&s=f9f716e38a8076846291b4176757c7f74c08ec45 https://preview.redd.it/how-to-implement-fractional-decimation-with-32spc-v0-fn0pnaeblsle1.png?width=1841&format=png&auto=webp&s=683f0970ec9f65f87e0c957771c6b347095a5ee8 frequency shift

I’m thinking if I can use two 16 SPC fractional decimators, where in one cycle, the first 16 data points are sent to the first fractional decimator, and the next 16 data points are sent to the second fractional decimator. This way, 32 IQ data points (32 SPC) can be processed in one cycle. However, I’m not sure how to program this, so I hope someone can help me, or if you guys have other ideas.

Any help appreciated. Best regards.