External Clock on FPGA

[JustinThomas]

I would like to sample my data based on an external clock on a FPGA board. I was thinking of using a timed loop with a DI line as external clock. The timed loop with iterate based on the clock rate of this DI line. I have not found any way of doing this.

Is this possible? or am I looking down the wrong path?

Any alternate suggestions would be most welcome

Regards,

Justin Thomas

[alexwarrior]

Hi Justin,

Can you explain a little more about what hardware you're using? I.e. what LabVIEW is running on, what FPGA, any other DAQ hardware you're using, etc.

Best,

- Alex

[JustinThomas]

QUOTE (alexwarrior @ Mar 17 2009, 10:26 AM)

Hi Justin,

Can you explain a little more about what hardware you're using? I.e. what LabVIEW is running on, what FPGA, any other DAQ hardware you're using, etc.

Best,

- Alex

I am using a 7811R board. My requirement is to read a digital data line at the rising edge of a digital clock line. The problem is the clock line is external and may vary. The requirement is similar to sampling on a DAQ board using an external clock.