OK I attached the whole Simulation VI. I deleted the most of the other stuff to make it easier to have a look at it. The FPGA VI is not attached, but what it does is very simple: It has two case structures which will be called over and over again. Both of these case structures who look almost the same are reading the PortA at the same time. Now this is what happens, if I start the simulation "current array index Kl_" and "... Kr_" are always the same. They show a sequenz like this:
0 () 6 () 4 2 1 7 6 4 2 0 6 4 2 ...
or a little bit different like this:
0 () 6() 4 2 0 6 4 2 0 7 5 ...
What I would expect is: 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1....
The brakets () show that the numbers in this case where moving too fast (why? I dont know). The other numbers later are changing, as specified with the delay, every 500ms.
I dont have a solution for this weird behaviour, but I found a workaround. I just changed one PortA blocks in the FPGA with another free port (e.g. PortB). And made another case frame in the simulation VI. Now everything works as expected.
PS.: Ignore the comment below my picture. It was generated from LabView.