Hi, I'm working on project involves implementing on Xilinx Spartan 3E FPGA. I've completed the design, compiled it, then tested it and everything is OK. When I started writing the final results to my boss I encountered unusual problem. The percentage of LUT consumed by the design is 123% (5734 out of 4656). How is that possible? Again everything is working fine but how come the FPGA compiler reports that 123% of the LUT is used ?! Where did (5734-4656 = 1078) LUT come from?. Compilation report is attached. Thanks in advance.
Compilation Report.txt