From what it sounds like, I bet that James' notion was spot-on: the last closing of the session was resetting the FPGA, which is fine but will not result in the FPGA restarting (and, as he noted, opening a session to a non-running FPGA VI is perfectly valid, it's just not running).
Ensure (at least) one of the following:
ensure that all closing sessions are not configured to reset the FPGA (and ensure that you do not abort the RT VI(s) that open the session(s))
configure the Open Sessions to force a download (if you do not need to maintain state in the FPGA from one opening of the sessions to the next)
On opening a session, force that the VI be running (and possibly filter the warning that occurs if the VI is already running)