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LabVIEW Information

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    LabVIEW 2009
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bkb2005's Achievements


Newbie (1/14)



  1. Now it seems like the bottleneck is the TC readings. The module is slated for 1200 S/s aggregate so I think the FPGA is waiting for the next scan value instead of sending duplicate results like the scan engine does.
  2. Here is a screenshot of my architecture. Please note this is only for the main chassis, and I haven't even gotten to the Expansion NI 9144. This is a DMA FIFO from Target to Host @ 1000Hz with 164 channels. This won't go anywhere close to 1000Hz, more like 100 Hz. Is this the standard way for logging data at the RT Target aside from streaming FPGA -> SD Card?
  3. So then what is the point of using LabVIEW real-time target? I can just run a Windows EXE on an Intel i7-980x six core processor and outperform it.
  4. This is something I can't find information for and is driving me crazy. I have a project where I'm accessing a cRIO with the NI Scan Engine. If I compile this to a Windows EXE file, what exactly is happening under the hood? Is this Windows EXE deploying real-time code to the cRIO and acting as a remote panel? Or is the actual logic running locally?
  5. I just compiled and tested 128 AI channels being sent through a FIFO @ 1000Hz to a real-time host. It works, very fast, no jitter/lag. Is there a limit on the number of FIFOs I can create? Just to clarify: 128 AI channels sent from FPGA to RT Host via DMA FIFO. I will need to create multiple FIFOs to get thermocouples and other such things across as well. I have also found something very interesting, the difference between a Thermocouple module and an AI module is the fixed-point data type. The size of data in bytes differs meaning you cannot combine an AI and TC reading into one array. they must be separated otherwise when the RT host reads the FIFO the data comes out all mangled into some strange typecasted format.
  6. Since I can't use one FPGA to access both chassis, I'm trying to create two FPGA VIs that use FIFOs back to the Host RT VI, which reads them in an alternating fasion and dumps to disk. Has anyone tried this?
  7. Hello, I have the following configuration: (1) cRIO 9025 controller on a NI 9118 8-slot Virtex-5 FPGA chassis, loaded with AI/TC modules (2) NI 9144 8-slot EtherCAT expansion chassis connected to the 9118 via EtherCAT, loaded with AI/TC modules I have been tasked with recording data on ALL of these channels at 1000Hz. I have been toying with various types of software architectures and cannot come up with an optimal system. I would like to log data directly to the cRIO 9025's on-board storage (and later retrieve via FTP). What is the best way to approach this? What type of architecture should I be using? Any help is very appreciated. Thanks!
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