Dvido

Hi, I'm having a strange problem with my FPGA code. I'm using a 7852R board with a PC. My goal is to simultaneously sample 2 Analog Inputs (AI), delay them by the same number of clocks, then perform some simple mathematical actions between each one of them and a file read from the PC (using a DMA FIFO) and then transmit them to 2 Analog Outputs (AO). I've divided the code into 2 "courses", both of them are completely identical - AI -> delay -> interaction with file read from PC -> AO. The strange thing is that they're not acting in the same way - actually what I see is that the change of the delay value impacts only one of them while the other one remains as it was. Per my understanding the analog output signals are supposed to be identical. As you can see in my code, I've wired the Timeout outputs of different FIFOs to DIOs for debug purposes - I can see that DIO14 isn't toggling at all while DIO7 (which is supposed to be completely identical) is working fine (toggling at the rate set by the host), Please help me to understand what is wrong and how can I fix it - it is very urgent. Also, I would appreciate some thorough explanation regarding the behavior of a FIFO (couldn't find any in the website) - for example: The behavior of the Timeout indicator, what happens if an element is read from a FIFO into an empty "thing" (like a "case") etc. My code is attached. Thanks in advance. Left_Right.zip

Hi all, I am new to LabView. I have a very urgent project (which seems to be very simple) but it's not working. I'm using the PXI-7831R board (will use the 7851R) and LabView 2010. The goal of my project is to continuously read TDMS files from the computer hard-drive and transmit them using 5 analog output channels. All the channels should be perfectly synchronized. First of all, since I'm working with very large data files, I'm parsing them into smaller files (offline, before the actual transmission). BTW I'm currently working on a version that will perform the parsing on-line - it's not ready yet but from what I see it won't solve the issues that I'm talking about. In order to transmit all the files simultaneously, I'm using a single DMA FIFO. I'm concatenating every value from the 5 files into an array, transmitting it to the FIFO and then on the FPGA side I'm sending each sample to a different analog output. I've encountered the following issues: 1. Transmission rate: Though the board spec (7831R) says that the transmission rate is up to 1M, I'm unable to transmit with a rate higher then ~550K without distorting the signal. For example, I use a 75KHz sine sampled at 500KS/sec rate. In that case, if I transmit the sine @1M I should see a 150KHz signal but what I actually see is a ~80KHz signal. 2. When I analyze the transmission spectrum (with MATLAB), I can clearly see 2 spikes at +/-7Hz around the signal. These spikes are extremely bad for my project. I analyzed the files that I recorded (before the transmission) and the spikes aren't there which means that they're caused by the DAC. I managed to get rid of the spikes by not limiting the FPGA clock, but in that case, as I mentioned earlier the signal frequency is wrong. I think that the 7Hz noise occurs due to the fact that the FPGA buffer is emptied and re-filled. When analyzing the transmission with MATLAB I can clearly see that every ~150ms some samples are missing from the transmission. I tried it change the FIFO size but it didn't help. My project is attached - please tell me what am I doing wrong. I will also appreciate a working example of transmitting at 1M (or any other rate) that was verified and prooved to be working fine. Thanks in advance DMA output - 5 channels working.zip