Dan_Mc

Problem understanding FPGA PID VI

The integral and derivative actions of PID do not seem to track equations shown in documentation.

Derivative – PV set using triangle wave 0 – 10 – 0 at approx. 1 Hz the derivative of PV should alternate between +20 v/s and -20 v/s. The PID output maxes out at +/- 1 when Kd is set to 128. (Kp = Ki = 0.) Based on documentation the PID output should be +/- 20 when Kd = 1, and then 20*128 = 2560 when Kd = 128. Not sure why the effective gain is so small.

Integral – The error is set by setting SP = constant = 10, and varying PV using triangle signal noted above. The error is then a triangle that varies from +10 to 0, again over ½ second. The integral, therefore, should be varying from +2.50 to -2.50 over the complete cycle.

 Issue 1: The integral effect on PID output does not change sign when error integral goes negative. It appears that there is some absolute value function that only allows positive integral action regardless of error integration.  Likewise, if Ki is set to negative number the integral PID action only goes in negative direction. This implies that as the PV crosses over the SP level the integral action will keep adding to PID output that will then drive PV further past SP.

Issue 2: Unlike the derivative effective small gain, the effective integral gain is very large. With the Ki set to the smallest number available using FP 16.8, (approx. .0039). the PID output varies from 0 – 12.5 with the actual integral varying from -2.5 to +2.5. Not sure why the effective gain is so large.

Under VI properties we set scale all objects on front panel as the window resizes, the icons do change their size but the font stays the same size. Is there a way that the font will change with the icon size?

Security is the main one, so they cant change it but I can

Dan

Opening and closing config files as a binary file but using the config VI’s to sort and Perce them.

I was told this can be done any one know how?

Study the sample tests and there content. I passed mine but the CLD was easier.

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Currently they are using Corelis HW/SW to write to it

And green hills to read it

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Flash Memory chip. Any pointers?

passed CLD 90%

Are you a software architect?

Are you a software architect?

I think I passed the CLD test at NI week, any suggestions ongetting ready for the CLA ?