I'm migrating this thread to LAVA from the Info-Labview list so that others can follow it...
I'm acquiring PCM encoded streams and decoding them and sending the results to an RT target in real time. (The decoded data must be sent every 2.5 ms.) I'm trying to implement this routine as many times as I can on a single board. Basically I'm running out of space. I'm trying to determine what coding techniques are the most efficient. And there doesn't seem to be any way to isolate a bit of code and benchmark how much of the FPGA it occupies, so it's a difficult process.
Also, I'm trying to achieve high speed in my processing. In this area I can isolate code and test it, but benchmarking every available coding option is a bit tedious. It would be nice to have some general guidelines.
Here are some examples of the questions I have:
1. It seems that the fastest way to send data from the FPGA to the RT target is to use a single IRQ on the FPGA, and then to post data word by word in a synchronous indicator. A synchronous indicator only updates once it has been read by the RT target. This technique is undocumented by NI, but one of their FPGA people showed it to me. I have found this to yield the highest transfer rates. It would be nice to understand why this is faster than sending the data in an array.
2. I have problems where my FIFOs become unlinked with the program and return random data, but there is no error. This I believe this unlinking is a bug that occurs when you rename an FPGA vi or copy it. Has anyone else experienced this?
3. When storing data temporarily, I use FIFOs. These can be created as flip-flops, look up table or block memory. I would like to know the trade off between speed and FPGA space when comparing flip-flops to block memory.
4. What is the penalty incurred for creating a subvi within FPGA code, both is terms of time and space?
5. How does saving data in a shift register compare with saving it in a fifo?
6. If I have a Boolean constant linked to 5 data sinks, should I separate this into five constants, thinking it will require less signal routing in the fpga, or link all sinks to the same constant?
7. If I send a U8 source into a U32 sink, I get the grey dot indicating a data type mismatch and Labview changes the data to the correct type for me. Is it more efficient to let labview perform the conversion, or should I insert a conversion node myself.
8. To what lengths should I go to avoid using case structures?
The FPGA code has its own rules and there seems to be very little documentation available to explain the optimal way of approaching common tasks. Any little tips and tricks that anyone has discovered would be very appreciated.
=]
matt
-----Original Message-----
From: Richard Jennings [mailto:Richard_Jennings@sandia.gov]
Sent: Monday, September 27, 2004 7:48 AM
To: Hill, Matt
Subject: Re: any NI-RIO/FPGA users out there interested in sharing
experiences?
Hi Matt,
What are you trying to do. I've been using LV FPGA for almost a year.
Richard
On Friday, September 24, 2004, at 09:37 AM, Hill, Matt wrote:
> Hi. I've been using NI's FPGA module (PXI-7831R Reconfigurable I/O)
> for 3 months now and it's definitely got it's own set of quirks.
> Anyone else out there using this product who's interested in
> discussing issues surrounding it?
> =]
> matt hill
> Denver, CO
> USA
>
>
>
