pendodecahedron

I have written some Verilog code for a watchdog timer, but on compliation all the states are synthesised away, so that when simulated it gets stuck in state 0 without doing any of the stuff in that state ! If anyone is willing to help here's the code : //iPAM controller watchdog timer //N Roberts //22/03/07 module iPAMWDT (iclock, sys_clk, error); input iclock; //iPAM clock in 250Hz input sys_clk; //System clock 50MHz output error; //Status of iclock for //reset module reg error; reg [2:0] state; //State variable reg count; //Counter variable always @ (posedge sys_clk) case (state) //Initialisation state 3'b000: begin count = 10; error = 1'b1; state = 3'b001; end //State to check pulse width of //high part of 'iclock' 3'b001: begin state = 3'b001; //Count decrement during //high part of cycle if (iclock & (count > 0)) count = count - 1; //Check for low part of cycle if ((!iclock) & (count > 0)) begin count = 10; state = 3'b010; end //Check for timeout if (count == 0) state = 3'b100; end //State to check pulse width of //low part of 'iclock' 3'b010: begin state = 3'b010; //Count decrement during //low part of cycle if ((!iclock) & (count > 0)) count = count - 1; //Check for high part of cycle if ((iclock) & (count > 0)) begin count = 10; state = 3'b001; end //Check for timeout if (count == 0) state = 3'b100; end //Error state remains in this state //until a reset occures 3'b100: begin state = 3'b100; error = 1'b0; //stay here if an error end default: begin state = 3'b000; end endcase endmodule Any suggestion greatfully received. I am using Quartus 5.0.

Hello new here i'm a masters student in Mechatronics at Leeds Unioversity and initialy came after searching for an FPGA forum, which I now cant find now I am registered !