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Hey, I have an application where I need to sample at a specific higher rate to calculate RMS values and feed some of my values over FPGA front panel objects to a fast loop on my RT and send the samples at a slower rate (triggered by a timer) over a DMA FIFO to slower loop. I Set the loop time to 10000 S/s and i'm filling up the DMA FIFO every 50 ms. The diagram looks something like this: My question is: does the FPGA code execute the auto-indexed FOR-Loop like the Non-FPGA Diagram would, where the single Trigger bool from the timer remains true for all cycles of the for-loop, OR do I need to make sure the "Triggered" condition of the case structure is there for all FOR-Loop cycles? Thanks, Robert
