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  1. Hi guys. This semester I'm starting a course system development for control and automation engineering, witch will be based on LabView. Therefore, my University doesn't have a NI hardware, even a MyRIO for us to test our VI and the teacher said that we should test our projects with our own Arduino... So, I have a little experience in Arduino and I know the basics for LabView. Now I'm in a point that I know that with Arduino I'll not take the best from LabView. I cannot even deploy a code to it. So, there is where my question comes in... I'm looking for a new board better then Ardui
  2. Hello. I need change some code for SbRIO-9626 with LabVIEW 2018. I have code from LabVIEW 2015. Right now I have only LabVIEW 2018. And I worked with it for SbRIO-9627. LabVIEW FPGA, LabVIEW Real-Time, NICRIO1800 driver istalled. And I install Xilinx ISE 11.5 Compilation Tool too. When I start compilation FPGA VI I got error about problem with compilation too (see attachment picture). Could you tell me how I can solve this problem? It is very important.
  3. Hi, I am trying to use image convolution inside FPGA. My Image size is around 6kx2k. The convolution is applied properly until 2600 pixels in x resolution. After that, the values seem to miss previous row data. In Detail: As convolution is matrix operation, image data needs to be stored for the operation. But it seems there is an inadvertent error storing only 2600 pixels per row inside FPGA. And hence the filtered output is calculated assuming these pixels to be 0. I have tried with different image sizes, different convolution kernels, and also in
  4. Hi, If I generate an FPGA IP core from my LabVIEW code, can I use it somehow in traditional FPGA development environments, such as Vivado? Thanks, David
  5. Hello everyone, I’m not sure which forum is the right one which is why I created two new topics with the same content (one in Embedded and one in VI Scripting) – so sorry for the spamming. I have two questions: How can I generate a cRIO project programmatically? How can I start the “Discovering Devices” tool of the Project Wizard automatically? At first I will describe a bit more what I really want to do: I’m about to write an auto coder which should create a complete new FPGA project on my cRIO system without any user input. In the
  6. Hello everyone, I’m not sure which forum is the right one which is why I created two new topics with the same content (one in Embedded and one in VI Scripting) – so sorry for the spamming. I have two questions: How can I generate a cRIO project programmatically? How can I start the “Discovering Devices” tool of the Project Wizard automatically? At first I will describe a bit more what I really want to do: I’m about to write an auto coder which should create a complete new FPGA project on my cRIO system without any user input. In the
  7. Hello everybody, I'm about to write an application that can create a complete new FPGA-Project for the cRIO-system automatically without any user Input. Before I ask my question directly, I will give you a few Information about the system and how it works at the moment. I'm working with a cRIO-system that can have different modules in different slots (max 8). That system should be universally usable which means I can replace one module with another one at the start up and create a complete new project with a different name. Most of the project works (I can find out in which slots wh
  8. Hello, everyone. Recently I came across one issue, that I solved within a couple of minutes in Simulink, but cannot crack for a couple of days in LabVIEW. It is a Rising integrator (model and plots from Simulink attached). Mod is the modulus function (i.e. remainder), the integrator reset is triggered by the external “Trigger” signal at 1 sec. After that, as you see the integrator generates a ramp signal. I was trying to represent the same behavior in FPGA LabVIEW in order to use it further on my cRIO. I’ve seen on the forum, that one of the most feasible solutions for the Quot
  9. Hi all, working on my first reconfigurable IO project using a PXI 7811R with LabVIEW RT. I am building a quadrature encoder counter using a couple of the NI examples, and was wondering if there were any caveats to changing it to use an I-64 as the counter output? The NI example uses a 32 bit integer for the count. In my version, I changed it to an I64 count output and added a speed (counting ticks between pulses) output as well. It seems to work fine, but would appreciate any cautions that experienced FPGA users might have. Neville. PS. Cross posted to info-LabVIEW as well.
  10. Hello, I'm currently encountering a problem when accessing FPGA indicator with "Reading/ writing a control" node The FPGA part acquires data every 10µs The RT part Read the indicator every 2000µs But when Running the VIs, I see that the elapsed time between 2 Readings of the indicator change from one iteration to another Can someone help me?
  11. Hi Folks, The scenario is, I have a sbRIO 9651 and a MPU 6050 (A IMU sensor). I would like to acquire sensor data in FPGA VI, stream it to RT VI for processing and analysis and view it from windows based VI. I came across certain problems which I wasn't able to figure out. I dont have the appropriate cable to interface the sensor yet, which I have ordered, to test the VI. 1. FPGA VI: The I2C Master VI outputs a array of 14 bytes raw data (6 bytes for Accelerometer, 6 bytes for gyroscope and 2 bytes for temperature). since the data can only be written element by element
  12. My setup is: - PXIe-1082 chasis - PXIe-7962R FlexRIO - custom MRF timing card I want to send data via the DStarB line from the custom FPGA to the FlexRIO. I am reading the DStarB line in my LV FPGA program. The problem I have is that I only get the data when the DStarB line goes from '0' to '1'. If I send two '1' after another I only get the first one, because I only recognize the positive front. I would wager that the backplane has a setting for this DStar lines. Some pull-downs or something... I cannot read the VI_ATTR_PXI_DSTAR_BUS a
  13. I'm at a loss for what could be happening so I'm hoping somebody else has done something similar. I am using LabVIEW 2015 SP1 with the FlexRIO 15.5 drivers with the 7935R and receive an internal software error when trying to compile the example project "NI793xR - MGT Aurora CLIP.lvproj" when generating intermediate files. The Error I'm getting is copied below. Error -250514 occurred at Possible reason(s): An AXI4-Lite address map element cannot fit in the specified address collection. Make sure that each address map elements' offset plus size does not exceed the address collection's
  14. Hi, I am quite familiar with different design pattern on LabVIEW but I am a newbie on FPGA design. I start working on a project for my own hobby using myRIO to control motor speed with PWM and read back encoder. This is the first part of my project and I plan to expand more later. This project will help me to get use to FPGA too. I am trying to learn a good design pattern by follow the template project which is "LabVIEW FPGA control on Compact RIO". In this template project, feedback value and control signal are analog channels and they connect directly with PID module in FPGA in a normal whi
  15. Hey guys, I'm trying to do some scripting on a Realtime-VI wich uses the FPGA Interface "Read/Write Control". I open a Reference to a VI containing a Read/Write Control, and when scrolling through the BD-Objects I find it with the class-name "nirviReadWriteControl". I used the "to more specific class"-VI to check wich class i can cast it to, and i tracked it down to be child of the GObject->Node Class. But i can't cast it to any of the childs offered in the class specifier constant. I also found out, that the "nirviReadWriteControl" is a xnode. I have never worked with those, is ther
  16. Hi FPGA expert. When I try “my way†of implementing a simple FPGA Analog Out VI, I run out of FPGA fabric (too may LUTs used). So what better way can I do this (if there is one), that don’t overuse my LUTs. My task is to: Make one analog measurement and control 2 analogue outputs that should be clocked out every time I get a digital trigger in. I’m running a sbRIO-9637 (Zynq7020) I’ve attached the simple application and I’m puzzled of what needs so many Look Up Tables (LUTs). Any suggestions? FPGATest.zip
  17. I have a system that composed of 1- NI-cRIO9014 2- Chassis (cRIO-9104) 3- Three Mods. NI9215 I use this system to capture 12 analog signals. What is the relation between sampling frequency defined by time delay in fpga.vi and the Requested number of Elements defined in FIFO?. When I use a time delay of 40us and Requested number of Elements 8191, it produces wrong data. When I use a time delay of 40us and Requested number of Elements 65535, it produces correct data.
  18. Hello all, a new control board based on the NI System on Module, formally sbRIO-9651, has been developed by an Italy based company. It is mainly devoted to industrial control as well as power electronics and drive applications. Each peripheral is supported by dedicated LabVIEW drivers as well as by demo projects... www.ped-board.com (UPDATE) Adapter Boards have been released for industrial and power electronics and drives applications: http://www.ped-board.com/adapter-boards/ Cheers, sirb
  19. I have a system that composed of 1- NI-cRIO9014 2- Chassis (cRIO-9104) 3- Three Mods. NI9215 The following are properties of my current FPGA Target Class: cRIO-9104 FPGA Device Information: Family: Virtex-II Type: xc2v3000 Speed Grade: -4 Package: fg676 Compiler Information: Version: Xilinx 10.1 Xilinx Options in Build Specifications: Supported Host Computer/FPGA Communication: Programmatic FPGA Interface Communication: Supported Interactive Front Panel Communication: Supported Number of Logical Interrupts: 32 DMA: Numbe
  20. Still learning about the cRIO, but thought I'd share some of what I've learned recently. Some background on what was going on... We had a driveline failure on two test stands out at customer site. There are sheer pins in the driveline designed to fail rather than send massive torque through a gear set in ways that is just BAD as it can lead to dynamic testing of the hard guarding (which is always fun!). Long story short, there was a failure more of the sheer pins that required detection of the sheer pins breaking. Worst case conditions is the break occurs at 6000 RPM and the only thing tha
  21. Hello everyone, I am working on Active Noise Cancellation project. I need to implement fixed point LMS code on FPGA target of myRIO 1900. I know , I can generate this using FPGA Target > IP Generator. I could do that, but I have to modify that code a litlle bit, as I will directly get the error e signal from microphone and there is no desired signal davailable. I did some decoding and understood a bit of how it is working, but still could not understand some essential part of it! Below I will attach, the FXP LMS vi . There are also two subVIs needed which I cannot include here but I
  22. I would like to design a FPGA module having an access to the resources like DIO,AIO or CAN which I can develop and test within one LabVIEW project and then use it within another. Idealy, I would like to have an API for RT implemented as a .lvlib and one VI which I have to drop on on my main FPGA vi. Currently, I have a .lvlib with virtual folders for RT and FPGA stuff. I have a few issues with this approach like requirement for changing FPGA typedef when I want to use it within another project and manual adding FIFO to the project. Well, I can live with this, but maybe you have a bette
  23. Hi all, I am trying to have an OOP based architecture inside RT ,where FPGA acquired values are used inside RT. So my plan is to have a generic base class upon which different systems(Child classes) are built. My child FPGA VIs will have additional controls in Front panel along with the common ones. So where can I put the FPGA ref? I cannot have it in base class since it will not bind all the controls. But if I have it in Child classes, how can I have the common functions in Base class? Looking forward to your suggestions guys..
  24. Question: How is 9*512 Discrete delays equal to ~410us? Context: We have found a solution to an offset problem between 2 sine waves, however we are unable to explain the delay calculations... (Someone else did the work a long time ago, now we need to explain the fix). There's 6us delay between the input Sinewave and the generated Sinewave from that input. Sinewave period is 416us (Figure 1). The Code works with 9 blocks of 512 Discrete Delays. 9*512*(1/80MHz) = 57.6us, but why is this working? Cannot Modify the code: The project is set and no code can be modified. Proje
  25. Hi all, I am trying to compile an FPGA code which results in the error as follows: ERROR:HDLCompiler:1566 - "C:\NIFPGA\jobs\t1y1Y1O_hxEgG35\NiFpgaAG_0000002b_SequenceFrame.vhd" Line 42: Expression has 32 elements ; formal ceioparameter0signal expects 24 How do I debug this. I have no idea about how xilinx compilation. Help me Thanks, Prabhu
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