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Found 40 results

  1. grjgrj

    LabVIEW 2018 and sbRIO-9626

    Hello. I need change some code for SbRIO-9626 with LabVIEW 2018. I have code from LabVIEW 2015. Right now I have only LabVIEW 2018. And I worked with it for SbRIO-9627. LabVIEW FPGA, LabVIEW Real-Time, NICRIO1800 driver istalled. And I install Xilinx ISE 11.5 Compilation Tool too. When I start compilation FPGA VI I got error about problem with compilation too (see attachment picture). Could you tell me how I can solve this problem? It is very important.
  2. prabhakaran

    FPGA Image Convolution error

    Hi, I am trying to use image convolution inside FPGA. My Image size is around 6kx2k. The convolution is applied properly until 2600 pixels in x resolution. After that, the values seem to miss previous row data. In Detail: As convolution is matrix operation, image data needs to be stored for the operation. But it seems there is an inadvertent error storing only 2600 pixels per row inside FPGA. And hence the filtered output is calculated assuming these pixels to be 0. I have tried with different image sizes, different convolution kernels, and also in different targets (cRIO 9030 and IC 3173). All results are same. I have attached a screenshot of FPGA VI and an example image. The example image shows an input image of 4000x2500 of same pixel value 16.The kernel is 3x3 of values 1 with divider=1. The RT image is processed using IMAQ convolute inside RT controller and has value 144 [(9*16)/1] for all pixels. But the FPGA processed image (zoomed in) has 144 until 2597 pixels and then 112 (7*16- showing 1 column of 2 rows missing) at 2598, 80 (5*16- showing 2 columns of 2 rows missing) at 2599 and 48 after that (missing 3 columns of 2 rows- current row is always present). This shows the data is missing from the previous rows after 2600 index. Is there some mistake in the code or any workaround available?
  3. tdavid

    LabVIEW IP core reuse

    Hi, If I generate an FPGA IP core from my LabVIEW code, can I use it somehow in traditional FPGA development environments, such as Vivado? Thanks, David
  4. Hello everyone, I’m not sure which forum is the right one which is why I created two new topics with the same content (one in Embedded and one in VI Scripting) – so sorry for the spamming. I have two questions: How can I generate a cRIO project programmatically? How can I start the “Discovering Devices” tool of the Project Wizard automatically? At first I will describe a bit more what I really want to do: I’m about to write an auto coder which should create a complete new FPGA project on my cRIO system without any user input. In the Project Wizard I want to run the “System Setup” from NI standalone. In that mask the NI project need some input like project type which is always a cRIO Embedded System. The next step is to insert an IP address to discover an existing system. As those two steps are every time with the same input, I want to give them those parameters so that everything runs automatically. Is there anybody who can help? Thanks a lot!!
  5. Hello everyone, I’m not sure which forum is the right one which is why I created two new topics with the same content (one in Embedded and one in VI Scripting) – so sorry for the spamming. I have two questions: How can I generate a cRIO project programmatically? How can I start the “Discovering Devices” tool of the Project Wizard automatically? At first I will describe a bit more what I really want to do: I’m about to write an auto coder which should create a complete new FPGA project on my cRIO system without any user input. In the Project Wizard I want to run the “System Setup” from NI standalone. In that mask the NI project need some input like project type which is always a cRIO Embedded System. The next step is to insert an IP address to discover an existing system. As those two steps are every time with the same input, I want to give them those parameters so that everything runs automatically. Is there anybody who can help? Thanks a lot!!
  6. Hello everybody, I'm about to write an application that can create a complete new FPGA-Project for the cRIO-system automatically without any user Input. Before I ask my question directly, I will give you a few Information about the system and how it works at the moment. I'm working with a cRIO-system that can have different modules in different slots (max 8). That system should be universally usable which means I can replace one module with another one at the start up and create a complete new project with a different name. Most of the project works (I can find out in which slots which module is placed and load the right VI's correctly) but there is one point which I really dislike: the user always has to give some input Information at the beginning of the creation and mostly that is the same like "Which type of project it should be" or "Which IP address should be used to find the system and the modules for each slot". The goal is that I can write down some specific arguments so the program is created automatically? Or - if there is no way to do this - a way that a second window is shown on screen to help the user through the creation process (for example that tells the user that the system need to be turned on that the project can find every single module)? English isn't my mother tongue, so please apologize if there are any mistakes in my spelling. Thank you very much for your help
  7. Hello, everyone. Recently I came across one issue, that I solved within a couple of minutes in Simulink, but cannot crack for a couple of days in LabVIEW. It is a Rising integrator (model and plots from Simulink attached). Mod is the modulus function (i.e. remainder), the integrator reset is triggered by the external “Trigger” signal at 1 sec. After that, as you see the integrator generates a ramp signal. I was trying to represent the same behavior in FPGA LabVIEW in order to use it further on my cRIO. I’ve seen on the forum, that one of the most feasible solutions for the Quotient & Remainder function (i.e., Modulus in Simulink) is the use of a while loop system with subtraction. But the behavior of the system is different since it generates a ramp signal after the reset is on, but it has a negative slope and saturates at -37k. Just to check in general how the approach works in LabVIEW, I’ve designed the second model with a Quotient & Remainder block (I know that for FPGA it is not the best option, plus I could not figure but how to use it with FXP values). But this model generates the output with a value of 5. Which is even more questionable. In this case, could you please advise what I am doing wrong with the FPGA code for the block? Since FPGA is the main reason, why I am looking for any options but not to use the Quotient & Remainder block. Thank you in advance. P.S. The models are designed in LabVIEW 2014 SP1. Integrator_SGL.vi Integrator_while_loop.vi
  8. Hi all, working on my first reconfigurable IO project using a PXI 7811R with LabVIEW RT. I am building a quadrature encoder counter using a couple of the NI examples, and was wondering if there were any caveats to changing it to use an I-64 as the counter output? The NI example uses a 32 bit integer for the count. In my version, I changed it to an I64 count output and added a speed (counting ticks between pulses) output as well. It seems to work fine, but would appreciate any cautions that experienced FPGA users might have. Neville. PS. Cross posted to info-LabVIEW as well.
  9. Hello, I'm currently encountering a problem when accessing FPGA indicator with "Reading/ writing a control" node The FPGA part acquires data every 10µs The RT part Read the indicator every 2000µs But when Running the VIs, I see that the elapsed time between 2 Readings of the indicator change from one iteration to another Can someone help me?
  10. Hi Folks, The scenario is, I have a sbRIO 9651 and a MPU 6050 (A IMU sensor). I would like to acquire sensor data in FPGA VI, stream it to RT VI for processing and analysis and view it from windows based VI. I came across certain problems which I wasn't able to figure out. I dont have the appropriate cable to interface the sensor yet, which I have ordered, to test the VI. 1. FPGA VI: The I2C Master VI outputs a array of 14 bytes raw data (6 bytes for Accelerometer, 6 bytes for gyroscope and 2 bytes for temperature). since the data can only be written element by element in a DMA FIFO, how can I stream an array to RT VI. I did an auto-indexed for loop to write data but I dont know if this will work. 2. RT VI: Initialization of MPU6050 is done here. It involves writing a byte array sequence to I2C Master VI to configure it and then a write-read(writing a register to read data from) process to acquire data. I am not sure how to do the write- read part. I was able to do it in myRIO RT Vi as it had clear APIs 3. The single process shared variable 'RT Stop' used for communication between loops in RT VI is written a value after the loop ends which I dont know as to why. The architecture is based on the Turbine example from cRIO developers guide. I am attaching the VIs for your reference. Please have a look into the code and let me know if you find anything that needs correction. I am totally new to Real time and FPGA programming. Thanks a ton Gokul first1.lvproj RT VI.vi FPGA acq.vi first1.lvproj
  11. leon43

    Cannot make DStar work

    My setup is: - PXIe-1082 chasis - PXIe-7962R FlexRIO - custom MRF timing card I want to send data via the DStarB line from the custom FPGA to the FlexRIO. I am reading the DStarB line in my LV FPGA program. The problem I have is that I only get the data when the DStarB line goes from '0' to '1'. If I send two '1' after another I only get the first one, because I only recognize the positive front. I would wager that the backplane has a setting for this DStar lines. Some pull-downs or something... I cannot read the VI_ATTR_PXI_DSTAR_BUS and VI_ATTR_PXI_DSTAR_BUS_SET attributes of the PXIe-7962 card from the LabVIEW program. The attributes are also not present in the VISA Interactive control Attributes list. Is there a problem, because the crate is not configured to work with my custom timing card? Or is the problem in the FlexRIO configuration? Do I need to enable something in the chassis settings in NI MAX? I went over everything but cannot find something useful. Do I need to configure the backplane with my timing card somehow? I am running out of ideas, so please do help.
  12. I'm at a loss for what could be happening so I'm hoping somebody else has done something similar. I am using LabVIEW 2015 SP1 with the FlexRIO 15.5 drivers with the 7935R and receive an internal software error when trying to compile the example project "NI793xR - MGT Aurora CLIP.lvproj" when generating intermediate files. The Error I'm getting is copied below. Error -250514 occurred at Possible reason(s): An AXI4-Lite address map element cannot fit in the specified address collection. Make sure that each address map elements' offset plus size does not exceed the address collection's total size. My goal is to replace the DRAM FIFO that is currently being used to write to Port 0 with a Count Up, Count Down, or PRBS signal. I was receiving the same compilation error after trying to make these changes. I tried to be very careful with what I replaced and was pretty confident that I hadn't touched any of the AXI4 functions. I tried compiling the example project because I was going to start over and make sure I had a good starting point. The example does run but that's using the bitfile that's already compiled. I've tried compiling using the cloud as well as a company compile server. I'm also installing software so I can try this on another computer. I don't think I need the tools locally for this but I might try installing those to double check. Pretty much out of ideas and wasn't able to find much online so any help would be appreciated. Matt J Edit: Same compilation error on second computer with local tools, both Windows 7.
  13. Hi, I am quite familiar with different design pattern on LabVIEW but I am a newbie on FPGA design. I start working on a project for my own hobby using myRIO to control motor speed with PWM and read back encoder. This is the first part of my project and I plan to expand more later. This project will help me to get use to FPGA too. I am trying to learn a good design pattern by follow the template project which is "LabVIEW FPGA control on Compact RIO". In this template project, feedback value and control signal are analog channels and they connect directly with PID module in FPGA in a normal while loop. The configuration are sent from host. In my prototype project, I already built FPGA module to drive PWM and read encoder using single-cycle time loop. I plan to use PID in real time code. If I want to follow the template design, I have to change the way I implement the code for FPGA and Real-Time. So right now, I am not sure what is a good design I should follow. If you have any advice, I will highly appreciate. Thank you very much!
  14. Hey guys, I'm trying to do some scripting on a Realtime-VI wich uses the FPGA Interface "Read/Write Control". I open a Reference to a VI containing a Read/Write Control, and when scrolling through the BD-Objects I find it with the class-name "nirviReadWriteControl". I used the "to more specific class"-VI to check wich class i can cast it to, and i tracked it down to be child of the GObject->Node Class. But i can't cast it to any of the childs offered in the class specifier constant. I also found out, that the "nirviReadWriteControl" is a xnode. I have never worked with those, is there a way to access theyr methods (I think they're called "abilities" for xnodes)? The goal of the application is to make the Read/Write Control display all available FPGA FP-Elements, and connect Controls/Indicators to them. There is the same Problem with the "Open FPGA Reference"-Node (Classname "nirviOpenFPGA"). I really hope somebody dealed with the xnodes a bit and can help me programmatically controlling them! Best, Trip
  15. MikaelH

    Running out of LUTs on Zynq 7020

    Hi FPGA expert. When I try “my way†of implementing a simple FPGA Analog Out VI, I run out of FPGA fabric (too may LUTs used). So what better way can I do this (if there is one), that don’t overuse my LUTs. My task is to: Make one analog measurement and control 2 analogue outputs that should be clocked out every time I get a digital trigger in. I’m running a sbRIO-9637 (Zynq7020) I’ve attached the simple application and I’m puzzled of what needs so many Look Up Tables (LUTs). Any suggestions? FPGATest.zip
  16. Fathy

    FIFO DMA Target to Host

    I have a system that composed of 1- NI-cRIO9014 2- Chassis (cRIO-9104) 3- Three Mods. NI9215 I use this system to capture 12 analog signals. What is the relation between sampling frequency defined by time delay in fpga.vi and the Requested number of Elements defined in FIFO?. When I use a time delay of 40us and Requested number of Elements 8191, it produces wrong data. When I use a time delay of 40us and Requested number of Elements 65535, it produces correct data.
  17. Hello all, a new control board based on the NI System on Module, formally sbRIO-9651, has been developed by an Italy based company. It is mainly devoted to industrial control as well as power electronics and drive applications. Each peripheral is supported by dedicated LabVIEW drivers as well as by demo projects... www.ped-board.com (UPDATE) Adapter Boards have been released for industrial and power electronics and drives applications: http://www.ped-board.com/adapter-boards/ Cheers, sirb
  18. Fathy


    I have a system that composed of 1- NI-cRIO9014 2- Chassis (cRIO-9104) 3- Three Mods. NI9215 The following are properties of my current FPGA Target Class: cRIO-9104 FPGA Device Information: Family: Virtex-II Type: xc2v3000 Speed Grade: -4 Package: fg676 Compiler Information: Version: Xilinx 10.1 Xilinx Options in Build Specifications: Supported Host Computer/FPGA Communication: Programmatic FPGA Interface Communication: Supported Interactive Front Panel Communication: Supported Number of Logical Interrupts: 32 DMA: Number of DMA Channels: 3 Multi-Element Access on Target: Not supported Peer-to-Peer Streaming: Not supported Type: Target to Host - DMA Control logic: Slice Fabric I am reading 12 Analog signals, I do not know what is the maximum value for Requested Number of Elements I can use? The General page help says a size of 2^M-1, What is M?
  19. Still learning about the cRIO, but thought I'd share some of what I've learned recently. Some background on what was going on... We had a driveline failure on two test stands out at customer site. There are sheer pins in the driveline designed to fail rather than send massive torque through a gear set in ways that is just BAD as it can lead to dynamic testing of the hard guarding (which is always fun!). Long story short, there was a failure more of the sheer pins that required detection of the sheer pins breaking. Worst case conditions is the break occurs at 6000 RPM and the only thing that we have already in the system is a 1 mm wide match mark on a 25 mm diameter disk. We found some laser sensors that could pick up the mark and bench tested the system. Everything looked good, so we integrated the bench test in the project, compiled everything and went to update the cRIO. This involved adding C series modules (electrician on site) and remote update of the cRIO application and bitfile through TeamViewer. Lessons learned... 1. Install the NI-RIO driver on a PC connected to the cRIO before it is 1000s of km away. Transferring 4GB of installer over a flakey TeamViewer connection is not recommended. 2. Replication and Deployment (RAD) utility works well for the RT portion, but may not be able to install a bitfile to the FPGA. 3. The example "Get & Set Real-Time System Image" can work when RAD does not. Building the example into an executable that can deploy a selected file is very useful. 4. It is possible to create a image using RAD without errors from an identical cRIO that does not have all of the C series modules. There will not be an error, however the image will not deploy/set (sometimes without an error message). 5. Shared variables can function correctly with different LabVIEW versions (person helping me accidentally converted everything to 2015 for the image that did eventually install). I'm sure I'm missing something, so would appreciate any insight people have.
  20. charansai

    Understanding FPGA FXP LMS.vi code

    Hello everyone, I am working on Active Noise Cancellation project. I need to implement fixed point LMS code on FPGA target of myRIO 1900. I know , I can generate this using FPGA Target > IP Generator. I could do that, but I have to modify that code a litlle bit, as I will directly get the error e signal from microphone and there is no desired signal davailable. I did some decoding and understood a bit of how it is working, but still could not understand some essential part of it! Below I will attach, the FXP LMS vi . There are also two subVIs needed which I cannot include here but I can add pictures of it if needed. I could not understand, how this algorithm performs the Estimated signal step viz. [ y(n) = x_temp(n) vector * w(n) vector ' ; ]. I marked the section of the code where I am facing some problem in the attached picture. The algorithm does not show any clue how it is performing these vector operations. I could not also understand, some logic with numbers that he has chosen like 8, 3 ,7 ,9 etc. Further clarifications on my understanding will be provided . Any help in this problem will be appreciated. PS: I could implement using memory blocks as basic array elements, like intialzing both x and w vectors. But eventually, I have to read and write several times, which is killing time. FXP LMS.vi
  21. BradPID

    Modular design approach for FPGA

    I would like to design a FPGA module having an access to the resources like DIO,AIO or CAN which I can develop and test within one LabVIEW project and then use it within another. Idealy, I would like to have an API for RT implemented as a .lvlib and one VI which I have to drop on on my main FPGA vi. Currently, I have a .lvlib with virtual folders for RT and FPGA stuff. I have a few issues with this approach like requirement for changing FPGA typedef when I want to use it within another project and manual adding FIFO to the project. Well, I can live with this, but maybe you have a better approach which you woluld like to share. I have found something like FPGA Advanced Session Resources https://decibel.ni.com/content/docs/DOC-35574 , but still I am not sure whether it something I am looking for. Any thoughts?
  22. prabhakaran

    FPGA Ref in LVOOP

    Hi all, I am trying to have an OOP based architecture inside RT ,where FPGA acquired values are used inside RT. So my plan is to have a generic base class upon which different systems(Child classes) are built. My child FPGA VIs will have additional controls in Front panel along with the common ones. So where can I put the FPGA ref? I cannot have it in base class since it will not bind all the controls. But if I have it in Child classes, how can I have the common functions in Base class? Looking forward to your suggestions guys..
  23. Question: How is 9*512 Discrete delays equal to ~410us? Context: We have found a solution to an offset problem between 2 sine waves, however we are unable to explain the delay calculations... (Someone else did the work a long time ago, now we need to explain the fix). There's 6us delay between the input Sinewave and the generated Sinewave from that input. Sinewave period is 416us (Figure 1). The Code works with 9 blocks of 512 Discrete Delays. 9*512*(1/80MHz) = 57.6us, but why is this working? Cannot Modify the code: The project is set and no code can be modified. Project Settings: The FPGA derived is at 80MHz, but the project Top-Level Clock seems to specify 40 MHz. The system automatically detects if there is an error greater than 5 degrees phase shift. Problematic: (http://prntscr.com/7ahhi5) Code: (http://prntscr.com/7ah2t3) Thanks
  24. prabhakaran

    FPGA Compilation Error 1566

    Hi all, I am trying to compile an FPGA code which results in the error as follows: ERROR:HDLCompiler:1566 - "C:\NIFPGA\jobs\t1y1Y1O_hxEgG35\NiFpgaAG_0000002b_SequenceFrame.vhd" Line 42: Expression has 32 elements ; formal ceioparameter0signal expects 24 How do I debug this. I have no idea about how xilinx compilation. Help me Thanks, Prabhu
  25. Hello All, I have implemented first order filter in Real Time and trying to implement in FPGA. Please attached code for your reference.

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