Complilation report problem

[bluesky96]

Hi, I'm working on project involves implementing on Xilinx Spartan 3E FPGA. I've completed the design, compiled it, then tested it and everything is OK. When I started writing the final results to my boss I encountered unusual problem. The percentage of LUT consumed by the design is 123% (5734 out of 4656). How is that possible? Again everything is working fine but how come the FPGA compiler reports that 123% of the LUT is used ?! Where did (5734-4656 = 1078) LUT come from?. Compilation report is attached. Thanks in advance.

Compilation Report.txt

[bmouring]

Hi, I'm working on project involves implementing on Xilinx Spartan 3E FPGA. I've completed the design, compiled it, then tested it and everything is OK. When I started writing the final results to my boss I encountered unusual problem. The percentage of LUT consumed by the design is 123% (5734 out of 4656). How is that possible? Again everything is working fine but how come the FPGA compiler reports that 123% of the LUT is used ?! Where did (5734-4656 = 1078) LUT come from?. Compilation report is attached. Thanks in advance.

If you look further down in the results (search for "Starting program map") you will see that you are well within the capabilities of the part, LabVIEW FPGA simply isn't reporting it correctly at the top (I'll look into this one for sure). I do notice however that it looks like you're using a large memory that doesn't seem to properly be mapped to a Block RAM, when I have a bit of time I'll look into why it's not being inferred properly. Out of curiousity, do you still have this project?