FPGA FIFO Question

[durnek60]

Hi!

I've a Host to Target DMA, that transfers data to the Upper loop. I'm counting the data arrivals and sending the data from upper loop to the lower loop by INNER_FIFO.

(After the specified data arrived in the upper loop more data will be transfered to OUTER_LOOP, but it can not be seen on picture.)

Placing an INNER_FIFO -> Get Number of elements to Read method in the INNER_WINDOW, I see, the remaining elemens in the fifo is highly increased by the time...

Maybe my calculation in the Inner_window loop takes so much time, so the fifo will be full?

INNER_FIFO (Target Scoped, Flip-Flops , 10.000 elements)

If it is, how can I reduce the calculation Time?

Another question, If I have a Target Scoped FIFO with only one Read and Write, shall I set it artbitrate Never?

Thank you!

(I can not post to NI forum, I got an Unexpected Error all time... )