Configuring a new system for a roller bench

[tato]

Hello all,

I'm doing an internship to renew the software and computer hardware of a rollerbench with NI and LabVIEW. The rollerbench remains unchanged.

The only experience I have with NI and LabVIEW is the Hands On of last thursday. So I hope you can help me sort some things out.

At this moment these requirements are fulfilled:

- 8x AI (250kS/s)

- 3x AO (100kS/s)

- 48x DIO

- 4x counters

- CAN-bus

The system also runs a PID controller with a max loop time of 0,5 ms.

I have configured some possibilities replacements:

• cRIO-9024 (800MHz) + chassis + 9205 (AI) + 9263 (AO) + 9493 (DIO) + 9862 (CAN) = 10k EUR
  
• cRIO-9074 chassis incl. (400MHz) + 9205 (AI) + 9263 (AO) + 9493 (DIO) + 9862 (CAN) = 5kEUR
  
• PXIe-8102 + chassis PXIe-6363 (32AI+48DIO+4AO)+ 8513 (CAN) = 10k EUR
  
• Dell Presision T5500 + PXIe-6323 (32 AI, 48DIO, 4AO) + 8513 (CAN) = 5k EUR
  

The most interesting system is according me the cRIO-9074, but my contact person at NI says it is possible too slow for my application with the high loop rate of the PID controller as main reason.

Normally, the second place is for the PC + PCI-e cards, but NI don't give any garantee it will work without problems. So the PXIe-configuration takes this place in as the reliability of the roller bench is highly recommended.

What's your opionion about this question and is there maybe a better configuration possible?

Thanks in advance.

tato

[PaulL]

Are you doing the PID on the RT side or the FPGA side? If you do this on the FPGA side, you might be able to achieve your 2 kHz loop rate. If you do this on the RT side, I would recommend a more powerful device. We use a cRIO-9074 with the PID loops on the RT side. The fastest loop, though, runs at 62.5 Hz, which is about as fast as we have been able to achieve with reliable performance with a cRIO-9074. The applications are fairly complex, though, and we the inputs come in over the network via shared variables.

I did a test where, as I recall, I was just testing shared variable communication (my memory is not so good here) and 2 kHz was the absolute limit, but 1 or 0.5 kHz was the meaningful limit where there weren't significant buffering delays. I know that's a sloppy answer, but it is something.

[tato]

Thank you for answering.

The choice of which side (RT/FPGA) I took, isn't yet decided, but RT seems easier than FPGA. Though, I don't have any experience with both.

I have almost decided that I would buy a PXI-8102, it's with dual-core, so LabVIEW can devide the tasks over the 2 cores.

[PaulL]

Yes, I would agree that it is easier to develop (and especially debug!) code on the real-time side.

I am guessing there are no environmental requirements that preclude the use of PXI. (I only ask because that is the primary reason we opted to work with cRIOs--they are specified to work in our environment.)