Götz Becker Posted December 3, 2004 Report Posted December 3, 2004 Hi, I just started my first testproject with the FPGA Modul 1.1. I made 2 loops which should transfer data using 2 FIFOs. But I just can Quote
Götz Becker Posted December 6, 2004 Author Report Posted December 6, 2004 Looks like my problem is similar to this: http://digital.ni.com/public.nsf/websearch...6256F4D00189B26 Not a "solution" I am happy with, but at least some info on the topic. Quote
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