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Digital Input Filter


ASTDan

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According to the specifications, the input delay time for the 9435 is 3 msec (2.8 msec in the manual). That means a signal must remain in the ON or OFF state for that amount of time before the device registers the transition. So, you effectively have that filter always enabled. It's just that you do not have the ability to easily change the time constant the way you do with the industrial digital I/O cards like the 6514. If your glitches are less than 3 msec long, you should be fine with the 9435. If they are longer than that, you will have to do some extra filtering in your LabVIEW diagram.

If you are using the 9435 in a cRIO, you can fairly easily create that same API behavior with your FPGA VI. If you are using the cDAQ, you would have to do it on the host.

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I have solved it in software using the timout eventI have the change detection digital read in an event loop. I store the digital data in a shift register in the event loop, and set the timout value to my filter time.

When a change is detected I set the timeout case in the event loop to my filter time.

If I don't see a change event my timeout event fires and sends the digital data stored in the shift register to my consumer loop. After the timeout event fires I set the timout to -1. A timout value is only trigged when I get a digital change event.

This seems to work well.

Hopefully NI will add programatic filtering on the 9435 16x16_smiley-wink.gif That is my wish

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