Fast sampling rate with slow module

[MichaDu]

Hi,

I'm using an FPGA-VI with high sampling rate to read samples from a module. Now I would like to install an additional module with a low sampling rate.

What is the better solution:

1. an additional loop with low sampling rate? The problem is that I am at the slice resource limit (about 95%) and in doubt that there is not enough space!

2. implementing the daq routine of the slow module inside the fast loop? Does this slows down the loop (that would be bad) or are there just multiple sampling values read (that would be ok for me)?

Looking forward for any tipps!

[Matthew Zaleski]

QUOTE (MichaDu @ Mar 3 2009, 07:48 AM)

Hi,

I'm using an FPGA-VI with high sampling rate to read samples from a module. Now I would like to install an additional module with a low sampling rate.

What is the better solution:

1. an additional loop with low sampling rate? The problem is that I am at the slice resource limit (about 95%) and in doubt that there is not enough space!

2. implementing the daq routine of the slow module inside the fast loop? Does this slows down the loop (that would be bad) or are there just multiple sampling values read (that would be ok for me)?

Looking forward for any tipps!

I can't answer most of your question. But are you sure you are at your slice limit? The compiler is an incremental optimizer. Once it gets your code to fit it stops optimizing for space. A better proxy is based on how long your compiles are taking. When compile times start rising a lot for small additions to the code, then you are getting close the limit of your particular FPGA.

[MichaDu]

QUOTE (Matthew Zaleski @ Mar 4 2009, 09:03 PM)

I can't answer most of your question. But are you sure you are at your slice limit? The compiler is an incremental optimizer. Once it gets your code to fit it stops optimizing for space. A better proxy is based on how long your compiles are taking. When compile times start rising a lot for small additions to the code, then you are getting close the limit of your particular FPGA.

I am using daq algorithms for 3 modules (32xAI,32x DI and 4xAO) in three loops. The new module is 8xAI. The compilation time is about 3 hours with about 95% slices used. Sometimes there are compile errors (timing constraints) so that I have to recompile several times.

Before adding the 32xDI module there was only about 60% slices used so I am in doubt that there is enough space for the new module. I am also using a simple user interface in the FPGA-VI with tab containers and dialog controls to make debugging more easy.