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About nishad

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    I've come back for more.

LabVIEW Information

  • Version
    LabVIEW 8.6
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  1. RTNEW.viFDAQFPGA.viThank you all for the suggestions. I have changed the RT VI so that the WSSRPM and ACC FIFO interrupts are acknowledged in parallel loops. I changed the FPGA VI to interrupt after a set number of acquisitions. This was beneficial in two ways. The interrupt generation frequency has been greatly reduced. When RT gets the interrupt, I know exactly how many values to read, and those number of values are already in the FIFO, meaning RT doesnt have to wait before reading the values. After these changes, the program has been working satisfactorily. But I have run the program only for a few mins each time. I would be grateful if you could just look through the code and verify it. If you could suggest any changes to make the programs better, I would greatly appreciate them. Thanks Nishad
  2. FDAQRT.viHey All I am working with a cRIO-9004. I wrote an FPGA VI to acquire data at different rates in parallel loops. The WSS-RPM loop samples 3 sets of data at 1500Hz while the Acc loop samples 5sets of data at 100HZ each. For each loop I am transferring the values to RT using DMA FIFO and generating a separate interrupt. For the RT program, I wrote code where RT waits for interrupt no 1 then reads the values from the DMA FIFO and acknowledges the interrupt then the same procedure is followed with the other interrupt. I am logging the data read from the FIFO to a tdms file and observed that I am losing some data. I fiddled around with the no of elements to be read from the FIFO on the RT side and got varying degrees of loss. Is this because the RT VI is executing strictly in parallel and hence always services interrupt 1 first, then zero hence leading to data loss?? Also this means that the interrupts from the FPGA aren't really working like interrupts but the situation is sort of similar to polling. I am not able to rectify this problem and I would be grateful if you could help me with the same. I know I need to change the code in my RT VI but dont know how to go about it.FDAQFPGA.vi I am attaching both the FPGA VI and the RT VI so that you can clearly understand the problem.
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