RTNEW.viFDAQFPGA.viThank you all for the suggestions.
I have changed the RT VI so that the WSSRPM and ACC FIFO interrupts are acknowledged in parallel loops.
I changed the FPGA VI to interrupt after a set number of acquisitions.
This was beneficial in two ways.
The interrupt generation frequency has been greatly reduced.
When RT gets the interrupt, I know exactly how many values to read, and those number of values are already in the FIFO, meaning RT doesnt have to wait before reading the values.
After these changes, the program has been working satisfactorily. But I have run the program only for a few mins each time.
I would be grateful if you could just look through the code and verify it. If you could suggest any changes to make the programs better, I would greatly appreciate them.
Thanks
Nishad