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leon43

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About leon43

  • Rank
    LAVA groupie

LabVIEW Information

  • Version
    LabVIEW 2014
  • Since
    2015
  1. It seems that there is some problem on my backplane. The DStar line works from timing to a card in some other slot. Thanks to both of you for your input.
  2. If I understand the article correctly then I have to push the clock out of the DStar A on my timing card to the FlexRIO? In other words. The FlexRIO DStar B input register is clocked with the DStar A clock?
  3. My setup is: - PXIe-1082 chasis - PXIe-7962R FlexRIO - custom MRF timing card I want to send data via the DStarB line from the custom FPGA to the FlexRIO. I am reading the DStarB line in my LV FPGA program. The problem I have is that I only get the data when the DStarB line goes from '0' to '1'. If I send two '1' after another I only get the first one, because I only recognize the positive front. I would wager that the backplane has a setting for this DStar lines. Some pull-downs or something... I cannot read the VI_ATTR_PXI_DSTAR_BUS a
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