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Ratataplam

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Everything posted by Ratataplam

  1. Thanks Infinitenothing
  2. Thanks at all, both solution works. My question is an academic question. If I connect the sine wave generator to AO port or to Multiply operator a "cast" (red dot) is used by LV. Now, I must certificated my project and the assessor could be ask something about the red dot so how I can demonstrate that I don't not loss the information ? One solution is the test as decribed by "infinitenothing" or logical approach as suggest by Jordan. Does exist the way to avoid the cast without change the HW settings? Regards
  3. Hi all, i try to generate a sinewave in FPGA (NI cRIO Platform), to do that I use the specific VI (Sine Wave Generator) for fpga to produce a sinewave in UINT16 data type. Unfortunatelly my AO module works with FXP data type (see attach) and I need to adaptd the UINT16 to AO module. A simple cast is not sufficent because I loss information, any suggestion ?
  4. Hi, simple the cRIO is already present in the lab :D
  5. thanks a lot, your suggestions have avoid several attempt
  6. Hi all, I need your opinion about a problem. I need to reproduce a data file on a cRIO. Typically the file is made of recorded data from the field with at least 2 columns : time and value. I would use a cRIO to reproduce the file and stimulate my target (device under test) with the same condition of the equipment on the filed. The idea is : 1) trasfer the file on cRIO file system and open it. 2) read the data from the file with Read Delimited Spreadsheet and save the value in an array 3) read the array, row-by-row, with an auto-indexed tunel loop 4) Inside the loop send the data, organized into a cluster, to cRIO FPGA via RT-FIFO 5) On FPGA keep in listen on the RT-read and get the message when ready Someone has experience in this case? Any suggestion? Thanks
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