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Everything posted by 锋

  1. In fact, if I input 10, it needs to be multiplied by a coefficient to get 10V. The only reason I use I64 point and FXP point is that the date type "DBL" is not allowed in FPGA.vi.
  2. I use 7851R card. Of course, I will share my project. You could check the "simple signal.vi" and "simple signal test.vi". I forgot to send you pictures which indicated the values all of these 8 line got are different when I stop the FPGA.vi. ZSF-motor.rar
  3. Thanks! I made a sine wave and tried your method, still failed. So maybe there is different configuration in the .lvproj? Is there any way to solve this kind of problem?
  4. Thank you very much! I did send single point from RT side to FPGA. Before I try using DMA FIFO, I tried two test methods. First I bundled 8 point as cluster and sent it to FPGA. Then unbundled it in FPGA. But the phase shift still existed. Then I transferred the case structure into FPGA, phase shift still couldn't be fixed. In fact, I test these 4 signal and found that all the values of them were different! I'm going crazy!
  5. The PC system is Windows 7.I use Labview-2012 to write this program. I'm a beginner to study Labview. I'll be grateful if anyone could help me on this problem which nagged me for 3 days. Thanks!
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