QUOTE(orko @ Jun 27 2007, 09:40 AM)
Thank you orko Now i'm sure that the error resulted from the code loaded on the FPGA board ,
i checked the VHDL code it's OK. However when i changed the VHDL process that is resposible for this problem to have double the period, the Labview VI didn't work [i.e simulation stops and a timeout error showed up]
thus, i have to change the Baud rate to fit the new values ....[period doubled then Baud rate should be Half of its value] now Labview back to life again and work But unfortunately with the same Problem .
This is because when i used factor two to reduce the baud rate I -- at the same time -- doubled the period so they cancel each other and back to the same Problem.
i don't know what Can i do ....??!!
do you have any idea .... !!
regards
Sherif Farouk (",)
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