How to improve performance with FPGA generate frequency.

[Thang Nguyen]

Hi,

I am working on a project with cRIO. My VI runs in FPGA.

What I do in PC is calculate the frequency then convert it to period and convert to uSec (multiply by 1,000,000). This value is sent to FPGA by the FPGA interface.

In FPGA, I just do as in the screenshot.

I still have some different in the value. The value I calculate is 60.4 Hz and the signal I received from the scop is 60.2 Hz. I just wonder if I can make it better. This lead to a different of 0.1 mph or 5 r/min depend on signal.

I highly appreciate any help.

Best regards,

Thang Nguyen

[Ryan Podsim]

The first this I would do is replace the divide by 2 with a Right Shift, as a divide is a very expensive operation on an FPGA. The next thing I would do is calculate Cycle Period in Tick before sending to the FPGA, as this would increase your resolution. Though the frequency to are dealing with that doesn't seem like it would have much of an effect.

[Thang Nguyen]

Thanks Ryan,

I decided to change the solution by passing the high ticks and low ticks value seperately. How do you think about my new solution?

Best regards,

Thang Nguyen

Edited December 3, 2009 by Thang Nguyen

[Ryan Podsim]

The nested loop seems a bit unnecessary, but you're on the right track.

Below is what I did. I don't have a counter that reads that low, accurately, but at 5kHz it right on the money. I did notice that it adds 2 counts, which gives you a correspondingly slower frequency. I'm sure that could be fixed.