Reading Multiple PWM Inputs

[Ananth]

I'm using the c-RIO 9004 with the 9014 chassis and LabVIEW 8.6.

I need to read and log 13 PWM inputs. I've thought about multiplexing the PWM inputs like http://zone.ni.com/devzone/cda/tut/p/id/3254.

But the problem with multiplexing the PWM is that I won't have all the data from the 13 inputs at the same instant which I need.

So I've decided to have 13 loops on the FPGA each of which wait for a rising edge and then a falling edge and write the Ton time into an indicator. There is another 14th loop which reads from these 13 indicators using a local variable and writes into a DMA FIFO. RT reads from the FIFO and writes into a TDMS file.

Is this the best way to do this? Am I unnecessarily taxing the FPGA?

The PWM inputs are all from an infrared temperature sensor which I'm using to measure tyre temperature, which is why they need to be logged at the same instant.

Thanks

Ananth

[viSci]

I think you are unnecessarily taxing your diagram real estate

You need to first come up with a performance spec - how fast do you need to sample your tire temp's (include the transducer response time also) Chances are this sampling rate will be glacially slow compared to

the performance of the FPGA. I would go with the mux'd version, it will probably give you sub us synchronization.

[hooovahh]

I would recommend the FPGA route. I recently setup an FPGA to have about 10 PWM inputs and outputs on each of the 4 connectors. Each of these 40 PWM signals could be setup for PWM input or PWM output. I then added some debouncing code for each of the 40 PWM inputs. After that I tried adding code to detect 100% or 0% duty cycle on the inputs and that is when I ran out of space on my 4M gate setup (there were a few other things on the card) So I removed some unnecessary code like not all PWM needed to be an input or an output so I removed the unnecessary bits and it fit with plenty of space to spare.

Each of the PWMs are being read all at the same time but they can all be in the same time loop (you don't need an individual loop for each PWM signal). Instead of waiting for a high or waiting for a low, you can use feedback nodes. I think NI had an example on this somewhere. There are 2 U32s for each PWM input and 2 U32s for each PWM output on the front panel. I realize this is probably where alot of my gate usage is going, but after investigating memory management in a timed loop I decided to just go with front panel controls because I knew it would work but it might not be the best way.

Attached is an example of reading or writing two PWMs with debouneing on a 7813R. I haven't compiled the FPGA, and I haven't test the code but this is the technique I used.

PWM FPGA Example.zip