FPGA - 2 parallel code chunks are acting strange

[Dvido]

Hi,

I'm having a strange problem with my FPGA code. I'm using a 7852R board with a PC. My goal is to simultaneously sample 2 Analog Inputs (AI), delay them by the same number of clocks, then perform some simple mathematical actions between each one of them and a file read from the PC (using a DMA FIFO) and then transmit them to 2 Analog Outputs (AO). I've divided the code into 2 "courses", both of them are completely identical - AI -> delay -> interaction with file read from PC -> AO.

The strange thing is that they're not acting in the same way - actually what I see is that the change of the delay value impacts only one of them while the other one remains as it was. Per my understanding the analog output signals are supposed to be identical. As you can see in my code, I've wired the Timeout outputs of different FIFOs to DIOs for debug purposes - I can see that DIO14 isn't toggling at all while DIO7 (which is supposed to be completely identical) is working fine (toggling at the rate set by the host),

Please help me to understand what is wrong and how can I fix it - it is very urgent.

Also, I would appreciate some thorough explanation regarding the behavior of a FIFO (couldn't find any in the website) - for example: The behavior of the Timeout indicator, what happens if an element is read from a FIFO into an empty "thing" (like a "case") etc.

My code is attached.

Thanks in advance.

Left_Right.zip