Image "Streaming" In FPGA

[AlexA]

Hey all,

I am using a PXIe-7965R in a PXIe-1073 Chassis. This box is connected to a computer running Labview RT via a MXI cable to a PCIe receiver card. The 7965R has a NI 1483 cameralink adaptor module plugged into it, this is in turn connected to a Photonfocus camera with an 80MHz pixel clock. 8bit pixel data is gathered at a rate of 100MHz, using at least 512 lines.

The problem is that the system bandwidth listed on the NI website for the PXIe-1073 Chassis is 250MB/s. To stream 8bit at 100MHz (if I just use a to host DMA FIFO) requires 800MB/s. So, I'm stuck with some architectural issues on top of some fundamental questions. Given that an RT system can't perform read operations as fast as the FPGA can perform writes, I think I'm always going to get write timeouts and data loss, would this be correct?

One solution, assuming that the aforementioned problem is not as important as I think it is, would be to use a really big DMA FIFO and only trigger the capture on a succesful read out, this has issues in that it wastes FPGA resources which I want to use for other image processing functionality (FFT's etc.).

An alternative solution (which I believe may not be possible after reading the help file) Is to use the onboard DRAM to store the images, then read out from it later at a slower rate. According to the help file, you can not use memory to transfer data between clock domains on the FPGA, is this the case when using DRAM?

Does anyone have any insight on this issue? I'm prepared to accept less than optimal streaming, (I'm thinking of bursts of high-speed images stored in DRAM and read out slowly) if it's possible, or am I stuffed?

Regards everyone,

Alex

[JoeC]

I know you issue all too well.

You are not going to get full image update rate from your existing system across your backplane. I would suggest doing an FFT on each image and passing up those results. As for your images, I would only transfer fractional portion of the images you are collecting. The amount you pass on is going to be based on the application.

Also, I don't know if they exist, but image compression on the FPGA may help with this as well.

I hope this helps.

[Gary Rubin]

<snip> To stream 8bit at 100MHz (if I just use a to host DMA FIFO) requires 800MB/s<snip>

I must be missing something. Isn't 8bits at 100MHz = 100MB/s? Generally, the MB is megabytes, while Mb is megabits.

[Jordan Kuehn]

I must be missing something. Isn't 8bits at 100MHz = 100MB/s? Generally, the MB is megabytes, while Mb is megabits.

I'll point out that if you use 100MiB/s I think you are correct. 800,000,000 b/s = 95.367MB/s where B = 8 b, KB = 1024 B, MB = 1024 KB. Not sure where 800MB/s came from.

//Ah I have it backwards. Technically 100MB/s is correct while traditionally 95.367MB/s would be used and 95.367MiB provides clarity. http://en.wikipedia.org/wiki/Mebibyte

Edited August 5, 2011 by jkuehn