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Jordan Kuehn

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Jordan Kuehn last won the day on October 30 2020

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About Jordan Kuehn

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    LabVIEW 2020
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  1. Software Engineer - LabVIEW Full Time Professional Norman, OK, US This position will be responsible for maintenance and development of software that is core to our Freedom Series Completion System. The ideal candidate will have demonstrable software programming capability (specifically in LabVIEW), control systems experience, mechanical aptitude, ability to direct others, and an ability to operate in a fast-paced environment. This position can be located anywhere in the United States, but will require some travel to Oklahoma City at the beginnin
  2. I have spent a lot of time with the RTI DDS toolkit and it is good. I’m using MQTT for a lot of similar use cases. I believe we chatted some time ago about this a little. However, I don’t think this or the messenger library are feasible with the expansion chassis (9147 in my case) unless I were to implement the communication protocol in their FPGA. I would be happy to be wrong here though.
  3. Following. Mostly because it's very common that I'll kick off an RT build and want to move on to working on the Host application. Or the other way around. IMO the different projects shouldn't block each other during a build, but I'm sure there's some linking thing that they didn't want to solve so instead they lock the entire IDE.
  4. @Omar Mussa Thank you for this detailed analysis. I've found that my testing in 2021 on LV 2020 almost exactly replicates your results. I found some code on the darkside from @smithd that doesn't fix this issue, but I then repurposed into a check before the read that prevents the system from repeatedly attempting to reconnect and then time out. It's not ideal in my use case, but is better than blocking timeouts from a few dozen individual reads in my application that bring it to its knees. I've found that this will reconnect if the system and SVE is present
  5. I have a request from non-LV programmers who are using the JSON output I am providing them to provide the schema so that they can ensure they are accurately parsing the data structure. I have used a tool similar to this: https://www.liquid-technologies.com/online-json-to-schema-converter to generate it, but it is imprecise. I’d prefer to just give them the typedef file, but they have no idea what to do with that.
  6. I skimmed through the comments and I hope this wasn't addressed. If so, my apologies. Is there a way to limit the number of decimal places stored in a double numeric? Also, is there a way to generate a JSON schema based on a LabVIEW data structure? Thank you for this excellent toolkit.
  7. Sorry to resurrect this thread, but I am unable to get the RAD utility to work on my 9147 expansion chassis. Any tips for getting this to work? I've tried multiple 9147s on multiple computers and networks. (Now to hijack after resurrecting) I'd like to streamline the entire base software loading package, but I can deal with that if needed. The biggest benefit I've got here is the deployment of modules/channels/scales. I have located /var/local/natinst/deployfwk/config/variables.xml and it appears that this file (or perhaps all the files in this directory) contains the module deployment in
  8. Ah yes, you are reminding me of some specifics regarding the modules accepting integers when used in the FPGA and if the calibration mode is set to "Raw". Here are some notes I have from working with a 9263 (quite some time ago) which should be similar. Note explicitly casting types in the host sine wave properties VI (first picture) that produces the properties for signal generation that are passed to the FPGA code (second picture). The FXP constants wired in to the casting configures the bit word lengths. https://www.ni.com/documentation/en/labview-comms/latest/data-ty
  9. Is your amplitude correct? It looks like you are trying to command nearly +/-2000V output. Also you have a lot of coercion dots with your fixed points. Try to get those to be consistent. It's not as important with floats and integers, but you can get some strange stuff going on depending on how the bits are allocated going from FXP to FXP.
  10. I've done some of this in the past (when SCC decided to "merge" my lvproj file), and it seemed straightforward enough. I think I recall the primary reason it is unsupported is because they can change the xml structure at will. Currently I have use for this because I have one cRIO on my desk to test with and another in a system to deploy to. If only we had a way to virtualize targets, but that's a different can of worms!
  11. I'm not surprised by this, but thank you for weighing in. Maybe when NXG reaches CG parity in 2050.
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