_Mike_ Posted April 4, 2019 Report Share Posted April 4, 2019 Hi all! Does anyone know how one can programmatically add a given chassis to a target and fill it with a set of C-modules and FIFOs? I attempt to programmatically create a bitfile for a target when I know the set of modules I want to install in e-rio based remote I/O system. I do have standardized vis for interfacing each module (via FIFOs). Quote Link to comment
JamesMc86 Posted April 4, 2019 Report Share Posted April 4, 2019 Not through the FPGA interface I'm afraid. You can if your using scan engine/ethercat (though I would have to look up the calls again) Quote Link to comment
_Mike_ Posted April 12, 2019 Author Report Share Posted April 12, 2019 Thanks for reply. However it's not that I want to detect actual layout. I have a textual description what modules should be at which slots from another team, and I would like to programmatically create a project and build a bitfile. Quote Link to comment
_Mike_ Posted April 29, 2019 Author Report Share Posted April 29, 2019 After consultation with @Steen Schmidt I've learned that there is no API to do it, and the way to create a project including target consisting of few c-modules from limited poll would be by directly examine project's xml file. I will go that way. Quote Link to comment
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