王佳 Posted yesterday at 02:22 PM Report Share Posted yesterday at 02:22 PM First of all my device is a CRIO-9043. I want to use one dimensional lookup table for interpolation in FPGA.vi, I am using U16 data type and one lookup table can store 40960 data and I need to store 7 million data. Currently I have inserted only 16 tables and the RAM resources are not enough. My compilation tells me that one lookup table takes up 19 RAM resources (my device has a total of 325 RAM resources). But on the lookup table it shows that one table uses only 80KB of storage, while on the official website the CRIO-9043 has a RAM size of 2G! I don't know how to solve this problem. Attached is my program, sorry it's only in Chinese! 15.vi Quote Link to comment
Rolf Kalbermatter Posted 23 hours ago Report Share Posted 23 hours ago 5 hours ago, 王佳 said: First of all my device is a CRIO-9043. I want to use one dimensional lookup table for interpolation in FPGA.vi, I am using U16 data type and one lookup table can store 40960 data and I need to store 7 million data. Currently I have inserted only 16 tables and the RAM resources are not enough. My compilation tells me that one lookup table takes up 19 RAM resources (my device has a total of 325 RAM resources). But on the lookup table it shows that one table uses only 80KB of storage, while on the official website the CRIO-9043 has a RAM size of 2G! I don't know how to solve this problem. Attached is my program, sorry it's only in Chinese! 15.vi 3.4 MB · 0 downloads Your mixing and matching two very different things. The 2GB RAM is the physical RAM that the CPU and the Linux OS can use. But the RAM in the FPGA that is used for Lookup Tables is a very different sort of RAM and much more limited. The 9043 uses the Xilinx Kintex-7 7K160T FPGA chip. This chip has 202,800 Flop-Flops, 101,400 6 input LUTs, 600 DSP slices and 11,700 kbits of block RAM or BRAM, which is what can be used for the LUTs. If you really need these huge LUTs, you'll have to implement them in the realtime part of the application program, not in the FPGA part. 1s Quote Link to comment
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