FPGA clock speed

[vronto31]

Hello ,

I am working on cRIO and wish to know this about FPGA.

What is the base clock of a FPGA chip( 40 MHz or 200 MHz).

If 40 MHz is base clock then how is 200 MHz derived from it. ( I mean ho we divide one clock tick into 5)

Awaiting a response.

Thanks

[njg]

QUOTE(vronto31 @ Nov 12 2007, 10:58 AM)

Hello ,

I am working on cRIO and wish to know this about FPGA.

What is the base clock of a FPGA chip( 40 MHz or 200 MHz).

If 40 MHz is base clock then how is 200 MHz derived from it. ( I mean ho we divide one clock tick into 5)

Awaiting a response.

Thanks

The base clock is 40 MHz. Other clock frequencies (2.5 - 210 MHz) can be generated via PLL in the FPGA. Clock options are (40 x num / denom) within the afore mentioned range, where num and denom are integers between 1 and 32.

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QUOTE (njg @ Nov 13 2007, 10:21 AM)

The base clock is 40 MHz. Other clock frequencies (2.5 - 210 MHz) can be generated via PLL in the FPGA. Clock options are (40 x num / denom) within the afore mentioned range, where num and denom are integers between 1 and 32.

Yeah, but I don't think you can run complicated algorithms on anything higher than 40MHz

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QUOTE (john@aleconsultants.com @ Jan 23 2009, 11:50 AM)

Yeah, but I don't think you can run complicated algorithms on anything higher than 40MHz

A little more detail:

The derived clock (e.g. 200 MHz) can only be used to drive a single cycle timed loop (SCTL) in the LV FPGA diagram. Anything that you put inside the SCTL needs to be able to run within the derived clock period of the loop, e.g. 5 ns for a 200 MHz clock rate. Therefore if you put more code into a SCTL, the maximum rate at which that SCTL can run will be lower.

A 200 MHz SCTL will in fact be able to run very little code, which will most likely be limited to Boolean logic. Doing any kind of numeric data processing will be limited to significantly lower rates with a maximum loop rate in the range of 40 -100 MHz depending on the complexity of the code. In fact, if your longest code path in the SCTL increases, the maxium loop rate may be less than 40 MHz.

Note that there are certain functions that are not supported in the SCTL at all as they take more than one clock cycle to execute.

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QUOTE (LV_FPGA_SE @ Jan 23 2009, 01:15 PM)

A little more detail:

The derived clock (e.g. 200 MHz) can only be used to drive a single cycle timed loop (SCTL) in the LV FPGA diagram. Anything that you put inside the SCTL needs to be able to run within the derived clock period of the loop, e.g. 5 ns for a 200 MHz clock rate. Therefore if you put more code into a SCTL, the maximum rate at which that SCTL can run will be lower.

A 200 MHz SCTL will in fact be able to run very little code, which will most likely be limited to Boolean logic. Doing any kind of numeric data processing will be limited to significantly lower rates with a maximum loop rate in the range of 40 -100 MHz depending on the complexity of the code. In fact, if your longest code path in the SCTL increases, the maxium loop rate may be less than 40 MHz.

Note that there are certain functions that are not supported in the SCTL at all as they take more than one clock cycle to execute.

Very nice response, nevertheless, I have been very impressed with what speed improvements I have gotten using LabVIEW and FPGA's versus my dual-core 3.0GHz Intel machine.

Do you know if the latest PXI FPGA solutions that use Xilinx Virtex-5 chips make any improvements on this?

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QUOTE (john@aleconsultants.com @ Jan 23 2009, 12:31 PM)

Do you know if the latest PXI FPGA solutions that use Xilinx Virtex-5 chips make any improvements on this?

Yes, the Virtex-5 based boards are able to run code at significantly higher loop rates then the older R series cards using the Virtex-2.

I tested one example to get some numbers. The example is a SPI generator based on a state machine in a SCTL. For the Virtex-2 board (7833R) the maximum rate (according to the simulation in the compiler) is 116 MHz, while for the Virtex-5 board (7842R) The maximum rate is 159 MHz.