Batch compile for FPGA?

[DaveKielpinski]

Dear all,

I have an FPGA VI with many subVIs in my project. I would like to compile the entire project at once, but I can't seem to find a way to do this. So right now I have to pull up 30+ subVIs individually and compile them at the rate of about one every 20 minutes, which is really inconvenient.

Is there any way to do a batch compile of my project?

Thanks,

Dave Kielpinski

(cross-posted to NI forums)

[Götz Becker]

QUOTE(DaveKielpinski @ Nov 14 2007, 10:35 AM)

I have an FPGA VI with many subVIs in my project.

As far as I know (last time I touched LV-FPGA was in 7.1.1), compiling subVIs of a FPGA-MainVI doesn´t help. Since the result of a subvi compiled separatly would always output a bitstream for the whole FPGA. The same intermediate HDL-Code from the subvi will normally end up different, when its implicitly compiled as part of the mainVI to a bitstream, due to timing and size constraints require other/more optimizations at low level. I don´t think there is a way to incrementally compile HDL-code below http://en.wikipedia.org/wiki/Register_transfer_level' target="_blank">RTL

Feel free to correct me

[DaveKielpinski]

QUOTE(Götz Becker @ Nov 15 2007, 06:17 AM)

Feel free to correct me

Actually, you are perfectly right. The bug I am trying to track down is not related to improper compiling - unfortunately!

Thanks,

Dave