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Both of your FIFOs are massive, both to and from the FPGA. They can be MUCH smaller. What does your compile report look like, can you post a screenshot? Yeah, problem seems to be distributed RAM LUT cells, of which you only have 11000 ont he device. Your two FIFOs to and from the FPGA can be way way smaller, like 50 elements. You have set them to use Block RAM but I don't think the compiler is doing that.2 points