KWaris

I am in a bit of dilemma here: I need to have a multiplot cursor, so my choice is mixed graph I need to select a plot by clicking on a plot which I had achieved using get plot at pos invoke node for the xy graph- although only with the support from the geniuses on lava forums . Unfortunately, such invoke node or property node does not exist for mixed graph. Now I am only allowed to choose one out of these two graphs for my application. Can I have a multiplot for xy graph or a property/invoke node with the likes of 'getplotatpos' for mixed graphs ? Best Regards K Waris

Savitzky Golay Point by Point filter is not only filtering the noise but also smoothening the curve. Wow! I had never known the filters in Labview Software working, today I have seen it. I am so glad

My data being acquired from a displacement transducer updates well in real time on the standard waveform chart. However I noticed in properties>>plots that I could only select one of the following Interpolation of plot: 0-None, 1-Stepwise, 2-Linear, 3-Stepwise horizontal, 4-Stepwise horizontally centered, 5-Stepwise vertically centered. Is it possible to do cubic spline interpolation or the smooth update with the waveform charts? Many thanks

I had never known that the controls inside the cluster contained in the 2d array were unavailable to be used in the Edit Event Handling for this case dialog box. So I just did my best to trigger the events for the boolean controls. Please see attached my attempt. I will be glad to know there is a better way to achieve this. Any ideas? Kind Regards Austin Triggering Events For Booleans in an Array.zip

I have got a waveform chart which I am trying to design myself. It looks very simple so I tried to design it. I have added in the attached vi both waveforms. The Waveform A is the one which I would like to look like Waveform Chart B. Any ideas? Kind Regards Austin Customizing waveform chart.vi

I have a requirement of displaying continuously the update of a signal against time. I have achieved this. Then ability to press a boolean pause button to pause the display which I have achieved this as well. Now I have been asked to allow putting the cursors on the chart so the delta between two points could be interrogated. I just vaguely looked at it and I am left wondering if this is achievable? I dont seem to be able to put cursors for a chart. It looks like these are only available for a graph. Is it possible to put cursors on a waveform chart? Many thanks Austin

'It is the integral term that dampens ringing and overshoot' When I started closed loop control, I started with the belief that P - controls the speed of the controller I - reduces the steady state error D - reduces the overshoot However in reality, after setting it all up, I found: When P was 1 -5, the system will overshoot and oscillate around the setpoint, Increasing it to 40 in my attached vi and giving it a small integral of 0.00000000003 reduced all oscillations and overshoot. And controller holds the output once the target setpoint is reached. Spot On, No issues. Derivative do nothing. ( I am slightly disappointed why things sometimes dont work as described in the textbooks). I cant see the band stop filter on the FPGA, is there a vi somewhere I can download? Alternatively, I could use the combination of low pass and high pass filter to achieve this? Please advise Many thanks Ok. Lets put in a 50 - 60 Hz filter on the input. How do we do it? In my FPGA, I have Analogue input node which is dragged from the project explorer onto the block diagram of FPGA. There is only a butterworth filter available on the FPGA and wiring the Analogue input to the input of the filter and configuring the filter had not given my satisfactory results in the past. I must admit I did not think hard the first time I tried it and just wired the inputs hoping things will work. Have you guys used this filter and does it work?

I haven't had a chance today to study in detail the frequency but it looks to me a 50 HZ signal. The signal range is +- 10V. Please find attached my PID vi. It doesn't have the deadband. I have modified NI standard express vi to achieve very low integral. My system wont respond to higher integrals. This datalogger is built into the same FPGA. I have also used an additional analogue output module and mounted on the electrical console some BNC connectors for my customer to use the external datalogger. Many Thanks PID.vi

My customer wants the following. Turn the power to the pc on, the labview application loads up and FPGA starts streaming the data to the windows pc straight away. And they dont want the labview project, they want the .exe file. I developed the applicaton, however bypassed the RT controller for any digital I/O and used RT only for analogues. To stream RT from FPGA to RT, I used DMA FIFO and used Network stream to stream to windows. I did simple build, deploy and run as start up. 3 years done, it still works a treat. Bingo! Now I need to design a control application for the same customer and create a signal and continously update the profile of this signal into FPGA. I designed the signal generator in windows, implemented it and found that the update rate was too low. In stead of having nice smooth curve, I must design the profile in the RT and implement PID in RT. I do however require to send some PID values, Output gain and some other binary signals from windows to RT. I am confident deploying the RT application containing the PID loop. However, when I add the shared variables to stream all the PID data from windows to RT and for other signals which require streaming from RT to windows, my application works only in the development environmet as long as the RT application is running and windows is running. This is still unacceptable to the end customer as he wants to just press the button in the morning and let it run for the entire day. When I do the same steps the system fails and NSV doesn't seem to be deployed(proved). I am sure people may have come acroos this before and will appreciate a great deal if some support is provided on this. Kind Regards Austin

I am nearly there. I designed an FPGA based PID closed loop control system, did all the scaling for the raw volts signals to make sense to my customer. Its works beautifully well as long as we see it working as a machine. But as soon as we put a 10kHZ datalogger to see the feedback and controller output, we start seeing an unstable control system. By bit of investigation, we found that putting this unstable controller output to the actuator unit could damage it. The cause of this unstability is the noise on the Temposonic Linear LVDT. I can see continuous fluctation when at position zero from -0.02 to 0.02. If I plot this voltage this draws into a sine wave. Consequently my controller output is a continous unstable signal. I believe I have done my bit as a Labview programmer working on the application. I however unfortunately hold the title Control/Instrumentation Engineer and customer is looking at me and I have given all the theories I had learnt in the university from the basic PID control theory, mathematical model, laplace transform to fuzzy pi controller. But at the end of the day I have got to fix it. However I dont seem to get to the bottom of this noise issue and eradicate it. I am seeing this noise pattern on all the analogue. Filter in FPGA doesn't seem to work. Wiring and screening all ok. Cant afford averaging and mean techniques for the control system as the system must respond for a very tiny change in distance. I still hope people in the world had designed fantastic control application using NI. I was just reading an article where somebody managed to hold and control the position of a vertical steel ball in space based on closed loop control system. I am attaching my FPGA vi here which I have used to achieve a very small value of integral gain. It works a treat. I think I need advice on designing some software/hardware filter here. Kind Regards Austin

The Event Structure are designed and used USUALLY to respond to the user interface actions. You can although use the timeout case for detecting hardware digital inputs. It may not therefore be suitable in this context. Can you detect the hardware in your setup as it stands now. Can you just wire a simple boolean indicator, change the stage of your digital input and see the response. Is so then just wire the simple case structure to the same wire which wires to the boolean indicator showing your digital input, Put an increment function inside the true case and the use shift register to count up to the previous value

Stripping the block diagrams? Please advise how to achieve it.

The initialization vi only calls UDP Open in the Initialize Case, then iterate to the next state where it writes a telegram to the instrument then iterate to the next state to read the response. Its a while loop which iterates fifteen time unless the UDP read vi reads the data within the timeout period specified. It appears as if sometimes it reads this test telegram and sometimes the UDP read function fails to read it. As I have the error cluster wired up to all subvis, the subsequent code doesn't execute and the error flows through the error clusters. One thing which is slightly out of the scope of this problem. I would appreciate if it could be commented as well. Why I dont see the Labview error dialog box in my executable but I see them while running the executable? Thx

Hello everybody. I developed the code, took me three months and turned out its very good. Does the job and customer very pleased as long as I am the first one to come up and turn the computer on. This is because I know a little secret to make my executable work. And that secret is to shut down the labview application, turn it back on, keep doing it until the computer establishes the communication based on UDP protocol with the instruments. This project is based on cRIO 9012 controller and 9112 FPGA chassis. Computer IP address: 192.168.0.180 Instrument A IP: 192.168.0.175 Instrument B IP: 192.168.0.165 Instrument A: Port labview uses on windows to write to this instrument is 4243 Instrument B: Port labview uses on windows to write to this instrument is 4243 Both Instruments are similar and listen using only 4242. This is a single block diagram architecture based on many loops and hosted on windows target.( I do sometime thinks that if I had 9014 controller, I could have implemented the whole software on Real time controller but thats beyond the scope of this problem.) I increased/varied the timeouts, made the while loops which deals with UDP communication during initialization iterate until communication is establish but to no avail. The conclusion is the following statement ' Sometimes when the labview application runs, a communication port on windows operating system may locks up. The only way to release the port is by shutting down the application completely and restarting it again'. I just dont want the end customer to start this mission critical application knowing that the instruments may not communicate on initialization and they may have to close the application few times before it starts kicking. Please help. These are famous error 56 and error 66 and I did everything for instance varying timeout values, waiting longer before quitting while loops but nothing worked. It could help if I just can programmatically determine if at a time windows port e.g 4243 is locked up?. If so, It will help further, if I could unlock the port? I am just talking vaguely and have very limited knowledge on network communication especially when windows home operating system is involved. I am just slightly worried that the customer waited so long and the whole software application works a treat except that there may be some occasional communication problems on initialization. Any comments will be very appreciated Kind Regards Austin

"Also, even if you could trigger a password later, there'd be nothing stopping your user from copying out the code form your diagram into another VI before the time limit expired" I am dealing with a customer who is different than the ones I had before. He likes to take all the block diagrams but refuse to pay once he has got all the code. If there is some kind of date trigger protection, next time he opens the block diagram, he may be prevented from seeing the block diagram. Just a thought! I am surprized this feature already does not exist. I dont think I could protect my code and get rewarded for my efforts on the current project. Not sure what to do. I still love labview to bits. its incredible.