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KWaris

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About KWaris

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LabVIEW Information

  • Version
    LabVIEW 2011
  • Since
    2009
  1. I am in a bit of dilemma here: I need to have a multiplot cursor, so my choice is mixed graph I need to select a plot by clicking on a plot which I had achieved using get plot at pos invoke node for the xy graph- although only with the support from the geniuses on lava forums . Unfortunately, such invoke node or property node does not exist for mixed graph. Now I am only allowed to choose one out of these two graphs for my application. Can I have a multiplot for xy graph or a property/invoke node with the likes of 'getplotatpos' for mixed graphs ? Best Regards K Waris
  2. Savitzky Golay Point by Point filter is not only filtering the noise but also smoothening the curve. Wow! I had never known the filters in Labview Software working, today I have seen it. I am so glad
  3. My data being acquired from a displacement transducer updates well in real time on the standard waveform chart. However I noticed in properties>>plots that I could only select one of the following Interpolation of plot: 0-None, 1-Stepwise, 2-Linear, 3-Stepwise horizontal, 4-Stepwise horizontally centered, 5-Stepwise vertically centered. Is it possible to do cubic spline interpolation or the smooth update with the waveform charts? Many thanks
  4. I had never known that the controls inside the cluster contained in the 2d array were unavailable to be used in the Edit Event Handling for this case dialog box. So I just did my best to trigger the events for the boolean controls. Please see attached my attempt. I will be glad to know there is a better way to achieve this. Any ideas? Kind Regards Austin Triggering Events For Booleans in an Array.zip
  5. I have got a waveform chart which I am trying to design myself. It looks very simple so I tried to design it. I have added in the attached vi both waveforms. The Waveform A is the one which I would like to look like Waveform Chart B. Any ideas? Kind Regards Austin Customizing waveform chart.vi
  6. I have a requirement of displaying continuously the update of a signal against time. I have achieved this. Then ability to press a boolean pause button to pause the display which I have achieved this as well. Now I have been asked to allow putting the cursors on the chart so the delta between two points could be interrogated. I just vaguely looked at it and I am left wondering if this is achievable? I dont seem to be able to put cursors for a chart. It looks like these are only available for a graph. Is it possible to put cursors on a waveform chart? Many thanks Austin
  7. 'It is the integral term that dampens ringing and overshoot' When I started closed loop control, I started with the belief that P - controls the speed of the controller I - reduces the steady state error D - reduces the overshoot However in reality, after setting it all up, I found: When P was 1 -5, the system will overshoot and oscillate around the setpoint, Increasing it to 40 in my attached vi and giving it a small integral of 0.00000000003 reduced all oscillations and overshoot. And controller holds the output once the target setpoint is reached. Spot On, No issues. Derivative
  8. I haven't had a chance today to study in detail the frequency but it looks to me a 50 HZ signal. The signal range is +- 10V. Please find attached my PID vi. It doesn't have the deadband. I have modified NI standard express vi to achieve very low integral. My system wont respond to higher integrals. This datalogger is built into the same FPGA. I have also used an additional analogue output module and mounted on the electrical console some BNC connectors for my customer to use the external datalogger. Many Thanks PID.vi
  9. My customer wants the following. Turn the power to the pc on, the labview application loads up and FPGA starts streaming the data to the windows pc straight away. And they dont want the labview project, they want the .exe file. I developed the applicaton, however bypassed the RT controller for any digital I/O and used RT only for analogues. To stream RT from FPGA to RT, I used DMA FIFO and used Network stream to stream to windows. I did simple build, deploy and run as start up. 3 years done, it still works a treat. Bingo! Now I need to design a control application for the same customer and
  10. I am nearly there. I designed an FPGA based PID closed loop control system, did all the scaling for the raw volts signals to make sense to my customer. Its works beautifully well as long as we see it working as a machine. But as soon as we put a 10kHZ datalogger to see the feedback and controller output, we start seeing an unstable control system. By bit of investigation, we found that putting this unstable controller output to the actuator unit could damage it. The cause of this unstability is the noise on the Temposonic Linear LVDT. I can see continuous fluctation when at position zero from
  11. The Event Structure are designed and used USUALLY to respond to the user interface actions. You can although use the timeout case for detecting hardware digital inputs. It may not therefore be suitable in this context. Can you detect the hardware in your setup as it stands now. Can you just wire a simple boolean indicator, change the stage of your digital input and see the response. Is so then just wire the simple case structure to the same wire which wires to the boolean indicator showing your digital input, Put an increment function inside the true case and the use shift register to count
  12. Stripping the block diagrams? Please advise how to achieve it.
  13. The initialization vi only calls UDP Open in the Initialize Case, then iterate to the next state where it writes a telegram to the instrument then iterate to the next state to read the response. Its a while loop which iterates fifteen time unless the UDP read vi reads the data within the timeout period specified. It appears as if sometimes it reads this test telegram and sometimes the UDP read function fails to read it. As I have the error cluster wired up to all subvis, the subsequent code doesn't execute and the error flows through the error clusters. One thing which is slightly out of the
  14. Hello everybody. I developed the code, took me three months and turned out its very good. Does the job and customer very pleased as long as I am the first one to come up and turn the computer on. This is because I know a little secret to make my executable work. And that secret is to shut down the labview application, turn it back on, keep doing it until the computer establishes the communication based on UDP protocol with the instruments. This project is based on cRIO 9012 controller and 9112 FPGA chassis. Computer IP address: 192.168.0.180 Instrument A IP: 192.168.0.175 Instrument B IP:
  15. "Also, even if you could trigger a password later, there'd be nothing stopping your user from copying out the code form your diagram into another VI before the time limit expired" I am dealing with a customer who is different than the ones I had before. He likes to take all the block diagrams but refuse to pay once he has got all the code. If there is some kind of date trigger protection, next time he opens the block diagram, he may be prevented from seeing the block diagram. Just a thought! I am surprized this feature already does not exist. I dont think I could protect my code and get rew
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